mapfile.c

realview22.rar

      if (acc_nMREQ(i)) {
        Hostif_ConsolePrint(top->hostif, "IS");
      } else {
        Hostif_ConsolePrint(top->hostif, "%c", acc_SEQ(i) ? 'S' : 'N');
      }

      if (cnt != 0) {
        Hostif_ConsolePrint(top->hostif, "=%d", cnt - 1);
        if ((acc_nSEQ(i) || acc_nMREQ(i)) && seq != cnt) {
          Hostif_ConsolePrint(top->hostif, "/%d", seq - 1);
        }
      } else
        Hostif_ConsolePrint(top->hostif, "=Abt");
    }
    list->access_counts[i]=0;
    /*
     * normally "counter" will be the number of cycles the access takes, so
     *   "counter-1" is the number of wait states.
     * if this would abort, "counter==0", so wait states becomes -ve - i.e. -1.
     * if a 16-bit sequential read to latched memory, then the value is -ve
     *   number of cycles. "counter-1" could only ==-1 iff counter=-0, 
     *   i.e. abort,
     *   so these -ve numbers don't overlap with the "abort" signal. The real
     *   number of wait states is "(-counter)-1" i.e. "-(-counter-1)-2"
     */
    list->counter[i]=counter-1; /* number of wait states, or special */
  }


  /* Ask the host to disable its underlying memory's RDIInfo. */
  if (!top->FailedToInstal)
  { 
      uint64 data = FALSE;
      uint32 ID[2]; ID[0]=MemPropertyID_BaseMemoryEnable; ID[1]=0;
      top->child.mem_info(top->child.handle,
                          ACCESS_WRITE|ACCESS_WORD,&ID[0],&data);
  }

  Hostif_ConsolePrint(top->hostif,"\n");

  return 0;
}


static void Mapfile_GetStatsFromMemDescr(RDI_MemAccessStats *stats,
                                         MemDescr *desc, double clk)
{
    int i;

    stats->Nreads=stats->Nwrites=stats->Sreads=stats->Swrites=0;
    stats->ns=stats->s=0;
  
    for (i=0;i<0x40;i++) { /* Only include MREQ ones. */
        double ns;
        unsigned long count=desc->access_counts[i];
        if (acc_READ(i)) {
            if (acc_SEQ(i))
                stats->Sreads+=count;
            else
                stats->Nreads+=count;
        } else {
            if (acc_SEQ(i))
                stats->Swrites+=count;
            else
                stats->Nwrites+=count;
        }

        if (desc->counter[i]>=0) {
            ns=((double)(count*(desc->counter[i]+1))*clk*1000.0);
        } else {
            ns=((double)(count)*clk*1000.0);
        }

        while (ns>1e9) {
            ns-=1e9;
            stats->s++;
        }

        stats->ns+=(unsigned long)ns;
        /*
         * Just in case this goes round more than once
         */
        while (stats->ns>(unsigned long)1e9) {
          stats->ns-=(unsigned long)1e9;
          stats->s++;
        }
    }
}



/*
 * Callback for telling about memory stats
 */
static const RDI_MemAccessStats *GetAccessStats(void *handle,
                                                RDI_MemAccessStats *stats,
                                                ARMword s_handle)
{
  MemDescr *desc;
  MapfileState *top=(MapfileState *)handle;

  desc = &top->desc;

  while (desc) {
    if (desc->desc.handle==s_handle) {
      Mapfile_GetStatsFromMemDescr(stats, desc, top->clk);
      return stats;
    }
    desc=desc->next;
  }

  return NULL;                  /* not found */
}


/*
 * Function to deal with RDI calls related to memory maps
 */

static int RDI_info(void *handle, unsigned type, ARMword *arg1, ARMword *arg2)
{
  toplevel *top = (toplevel *)handle;
  switch (type) {
  case RDIMemory_Access:
    if (GetAccessStats(handle,(RDI_MemAccessStats *)arg1,*arg2))
      return RDIError_NoError;
    else
      return RDIError_NoSuchHandle;
    
  case RDIMemory_Map: {
    int n=(int)*arg2;
    RDI_MemDescr *p=(RDI_MemDescr *)arg1;
    while (--n >= 0 && !top->FailedToInstal)
      if (InstallMemDescr(handle,p++,NULL)!=0)
        return RDIError_Error;
  }
    return RDIError_NoError;

  case RDIInfo_Memory_Stats:
    return RDIError_NoError;

  case RDICycles: {
      if(top->num_regions != 0)
      {
          MapfileState *top=(MapfileState *)handle;
          ARMTime idle;
          /* Fix up NumScycles and NumNcycles */
          Mapfile_ReadCycles(handle);
          
          ARMul_AddCounterValue64(NULL, arg1, arg2, top->cycles.NumScycles);
          ARMul_AddCounterValue64(NULL, arg1, arg2, top->cycles.NumNcycles);
          if (!(top->prop & MAP_HARVARD) && (top->prop & MAP_AMBABUSCOUNTS)) {
              idle = top->cycles.NumIcycles + top->cycles.NumCcycles;
              ARMul_AddCounterValue64(NULL, arg1, arg2, idle);
          } else {
              idle = top->cycles.NumIcycles;
              ARMul_AddCounterValue64(NULL, arg1, arg2, top->cycles.NumIcycles);
              ARMul_AddCounterValue64(NULL, arg1, arg2, top->cycles.NumCcycles);
          }
/*           if (top->prop & MAP_COUNTWAIT) */
          {
              ARMul_AddCounterValue64(NULL, arg1, arg2, top->d.wait_states);
              if (top->prop & MAP_HARVARD) {
                  ARMul_AddCounterValue64(NULL, arg1, arg2, top->i.wait_states);
              }
          }
          ARMul_AddCounterValue64(NULL, arg1, arg2, top->cycles.Total);
          if (top->prop & MAP_SPOTISCYCLES) {
              idle -= top->IS_cycles;
              ARMul_AddCounterValue64(NULL, arg1, arg2, idle);
          }
#ifdef BadPlan /* We add these in a new tab instead */
          if (top->mf_MapFileLoaded) { /* If we loaded our own mapfile under RVD. */
              /* Add all the values from the regions. */
              xxxx;

          }
#endif
      }
      
      break;
  }
  case RDIRequestCyclesDesc: {
      if(top->num_regions != 0)
      {
          MapfileState *top=(MapfileState *)handle;
          int  retVal = RDIError_UnimplementedMessage;
          top->mf_CycleNames[10]="IS_Cycles";
          if (top->prop & MAP_HARVARD) {
              if( top->memtype == ARMul_MemType_StrongARM) {
                  top->mf_CycleNames[1]="Core_ID";
                  top->mf_CycleNames[0]="Core_IOnly";
                  top->mf_CycleNames[2]="Core_Idles";
                  top->mf_CycleNames[3]="Core_DOnly";
              } else {
                  top->mf_CycleNames[1]="ID_Cycles";
                  top->mf_CycleNames[0]="IBus_Cycles";
                  top->mf_CycleNames[2]="Idle_Cycles";
                  top->mf_CycleNames[3]="DBus_Cycles";
                  ARMulif_ReadCycleNames(&top->mf_CycleNames[0],16,
                                         top->memtype,top->config);
                     
              }
            
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2, 
                          top->mf_CycleNames[1] /*"ID_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2, 
                          top->mf_CycleNames[0]/*"IBus_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[2]/*"Idle_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[3]/*"DBus_Cycles"*/), retVal);
          } else if (top->prop & MAP_AMBABUSCOUNTS) {
              top->mf_CycleNames[1]="S_Cycles";
              top->mf_CycleNames[0]="N_Cycles";
              top->mf_CycleNames[2]="A_Cycles";
              ARMulif_ReadCycleNames(&top->mf_CycleNames[0],16,
                                     top->memtype,top->config);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[1]/*"S_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[0]/*"N_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[2]/*"A_Cycles"*/), retVal);
          } else {
              top->mf_CycleNames[1]="S_Cycles";
              top->mf_CycleNames[0]="N_Cycles";
              top->mf_CycleNames[2]="I_Cycles";
              top->mf_CycleNames[3]="C_Cycles";
              ARMulif_ReadCycleNames(&top->mf_CycleNames[0],16,
                                     top->memtype,top->config);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[1]/*"S_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[0]/*"N_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[2]/*"I_Cycles"*/), retVal);
              ACDTEST(ARMul_AddCounterDesc(
                          NULL, arg1, arg2,
                          top->mf_CycleNames[3]/*"C_Cycles"*/), retVal);
          }
/*          if (top->prop & MAP_COUNTWAIT)  */
          {              
              if (top->prop & MAP_HARVARD) {
                  ACDTEST(ARMul_AddCounterDesc(NULL, arg1, arg2, "D_Wait_States"), retVal);
                  ACDTEST(ARMul_AddCounterDesc(NULL, arg1, arg2, "I_Wait_States"), retVal);
              } else {
                  ACDTEST(ARMul_AddCounterDesc(NULL, arg1, arg2, "Wait_States"), retVal);
              }
          }
          ACDTEST(ARMul_AddCounterDesc(NULL, arg1, arg2, "Total"), retVal);
          if (top->prop & MAP_SPOTISCYCLES) {
              ACDTEST(ARMul_AddCounterDesc(NULL, arg1, arg2, "True_Idle_Cycles"), retVal);
          }
#ifdef NotHere /* We use a separate tab in RVD */
          if (top->mf_MapFileLoaded) { /* If we loaded our own mapfile under RVD. */
              xxxx;
          }
#endif
      } 
  break;
  }

  default:
    /* check for capability messages */
    if (type & RDIInfo_CapabilityRequest)
      switch (type & ~RDIInfo_CapabilityRequest) {
      case RDIMemory_Access:
      case RDIMemory_Map:
      case RDIInfo_Memory_Stats:
        return RDIError_NoError;

      default:
        break;                  /* fall through */
      }
    break;
  }
  return RDIError_UnimplementedMessage;
}


static void Mapfile_Reset(MapfileState *top);

/*
 * Other ARMulator callbacks
 */

/* Listen for EndiannessChanged Event */
static unsigned Mapfile_ConfigEvents(void *handle, void *data)
{
  MapfileState *top=(MapfileState *)handle;  
  ARMul_Event *evt = (ARMul_Event *)data;
  if (evt->event == ConfigEvent_Reset)
      Mapfile_Reset(top);
  if (evt->event == ConfigEvent_EndiannessChanged)
  {
      top->read_bigend = (!!evt->data1 != HostEndian) ? 3 : 0;
      if (!(top->prop & MAP_FIXEDSEX))
          top->write_bigend = top->read_bigend;
#ifdef VERBOSE_ENDIAN
      printf("\nMapfile read_bigend:=%08lx write_bigend:=%08lx "
             "evt->data1:%08lx HostEndian:%08lx\n",
             (unsigned long)top->read_bigend,
             (unsigned long)top->write_bigend,
             (unsigned long)evt->data1,
             (unsigned long)HostEndian);
#endif  
      top->byteAddrXor = ( top->read_bigend != HostEndian ) ? 3 : 0;
      top->hwordAddrXor = ( top->read_bigend != HostEndian ) ? 2 : 0;
  }
  if(evt->event == DebugEvent_RunCodeSequence)
  {
      /* save cycle counts */
      top->saved_cycles = top->cycles;      
      top->saved_IS_cycles = top->IS_cycles;
      top->saved_d = top->d;
      top->saved_i = top->i;
  }
  if(evt->event == DebugEvent_EndCodeSequence)
  {
      /* restore cycle counts */
      top->cycles = top->saved_cycles;
      top->IS_cycles = top->saved_IS_cycles;
  }
    
  return FALSE;

}

static void Mapfile_Reset(MapfileState *top)
{
    MemDescr *desc,*next;
    int i;
    memset(&top->cycles,0,sizeof(top->cycles));
    top->d.wait_states = 0;
    top->d.cnt = 0;
    top->i.wait_states = 0;
    top->i.cnt = 0;
    top->IS_cycles = 0;
    
    /* Clear the memstats ( memory_statistics ) data fields .
       This happens on startup, load, reload. 
       */
    for (desc = &top->desc; desc != NULL; desc=next) 
    {
        next=desc->next;
        for (i=0; i < 0x60; i++)
        {
            desc->access_counts[i] = 0;
        } /* end for i=0 */

        desc->stats_are_valid = FALSE;
    } /* end for desc=top */
}

/* NB This should memcpy to &regval->reg64, when RVDebugger
 * allows 64-bit 'registers' from a simulator,
 * to avoid aligement-problems.
 */

static SimabsRegisterAccess Mapfile_SimReg;
static SIM_ERR
Mapfile_SimReg( void* handle, bool_int reg_read,
                uint32 reg_num,
                REGVAL* regval, uint16 size )
{
    NumState *num_state = (NumState *)handle; 
    /*  MapfileState *state = num_state->state; */
    MemDescr *desc = num_state->md;

    UNUSEDARG(size); /* should be 4 (or, later, 8)! */

  if(reg_read)
  {

    if (!desc->stats_are_valid)
    {
      Mapfile_GetStatsFromMemDescr(&desc->stats,
                                   desc, num_state->clk);
      desc->stats_are_valid = TRUE;
    }
    switch(reg_num & 0x1f)
    {
    case 0: /* Address */
        assert(size==4);
        regval->reg32 = desc->desc.start; break;
    case 1: /* Limit */
        assert(size==4);
        regval->reg32 = desc->desc.limit; break;
    case 2: /* Width */
        assert(size==4);
        regval->reg32 = 1<<(desc->desc.width-BITS_8); break;
    case 3: /* Access */
        regval->reg32 = desc->desc.access; break;
    case 4: /* N-Reads */
        regval->reg32 = desc->stats.Nreads; break;
    case 5: /* S-Reads */
        regval->reg32 = desc->stats.Sreads; break;
    case 6: /* N-Writes */
        regval->reg32 = desc->stats.Nwrites; break;