validate.c

realview22.rar

       if (howlong == 0) {
           ARMulif_SetSignal(&state->coredesc, ARMSignal_IRQ, Signal_On);
       }
       else {
        {
            Validate_ScheduleUnretractable(
                &state->coredesc,DoAIRQ,state,cycle_count + howlong,0);
        }
       }
       return ARMul_CP_DONE;
  case 3: 
       ARMulif_SetSignal(&state->coredesc,ARMSignal_FIQ, Signal_Off);
       return ARMul_CP_DONE;
  case 4: 
       ARMulif_SetSignal(&state->coredesc,ARMSignal_IRQ, Signal_Off);
       return ARMul_CP_DONE;
  case 5: /* Reset Timer */
       state->FRTimer = cycle_count;
       /* DRS 2001-01-16
        * TC-32 for V6! */
       state->ValCP5Reg[BITS(12,13)] = (ARMword)cycle_count;

       return ARMul_CP_DONE;
  case 6: 
       timeNow =  cycle_count;
       if ( state->FRTimer < timeNow ) {
         state->ValCP5Reg[BITS(12,13)] = 
             ((ARMword)(timeNow-state->FRTimer) & 0xFF)-1; /* ? really?*/
       }
       else {
         /* ARMul time has rolled over */
           state->ValCP5Reg[BITS(12,13)] = 
             (ARMword)(((2^32)-state->FRTimer )+timeNow) &
             0xFF;
       }
       return ARMul_CP_DONE;

  case 7:
       if (howlong == 0) {
           DoASE(state);
       }
       else {
           Validate_ScheduleUnretractable(&state->coredesc,
                                         DoASE,state,
                                         cycle_count + howlong, 0);
       }
       return ARMul_CP_DONE;

  case 8:
       ARMulif_SetSignal(&state->coredesc,ARMSignal_SE, Signal_Off);
       return ARMul_CP_DONE;
  case 0xE:
      return ARMul_CP_DONE;


  case 0xf:
       if (howlong == 0) {
         DoAReset(state);
       }
       else {
        {
            Validate_ScheduleUnretractable(
                &state->coredesc,DoAReset,state, cycle_count + howlong, 0);
        }

       }
      return ARMul_CP_DONE;
  default:
      return ARMul_CP_CANT;
  }
}

 
/* CP7 CDP instruction - behaviour not checked*/ 
static int CP1CDP(void *handle, int type, ARMword instr, ARMword *dummy)
{
  ValidateState *state=(ValidateState *)handle;
  ARMTime cycle_count = GetCycleCount(state);
  (void)dummy;
  return DoCDP(handle, type, instr, cycle_count, 
               CheckBusyCycles(handle, CP1_WAIT_COUNT), &state->CP1Busy);
}

/* CP7 CDP instruction - behaviour not checked*/ 
static int CP3CDP(void *handle, int type, ARMword instr, ARMword *dummy)
{
  ValidateState *state=(ValidateState *)handle;
  ARMTime cycle_count = GetCycleCount(state);
  (void)dummy;
  return DoCDP(handle, type, instr, cycle_count, 
               CheckBusyCycles(handle, CP3_WAIT_COUNT), &state->CP3Busy);
}

/* CP7 CDP instruction - behaviour not checked*/ 
static int CP7CDP(void *handle, int type, ARMword instr, ARMword *dummy)
{
  ValidateState *state=(ValidateState *)handle;
  ARMTime cycle_count = GetCycleCount(state);
  (void)dummy;
  return DoCDP(handle, type, instr, cycle_count, 
               CheckBusyCycles(handle, 0), &state->CP7Busy);
}

/* CP8 CDP instruction - behaviour not checked*/ 
static int CP8CDP(void *handle, int type, ARMword instr, ARMword *dummy)
{
  ValidateState *state=(ValidateState *)handle;
  ARMTime cycle_count = GetCycleCount((ValidateState*)handle);

  int rv = DoCDP(handle, type, instr, cycle_count, 
               CheckBusyCycles(handle, 0), &state->CP8Busy);

  (void)dummy;
  /* CDP COPRO,2,c0,c0,c0,1
   * cdp p8, OP1, CRd, CRn, CRm, OP2
   * BitFields:
   * 23:20 OP1 - determines the operation.
   * 19:16 CRn
   * 15:12 CRd - Which cp reg. For some reason, only 4 registers are supported.
   * 11:8  CPnum (==5)
   * 7:5   OP2
   * 3:0   CRm
   */
  if (rv == ARMul_CP_DONE)
  {
      /* If OP1==2 then bounce next, even in privileged modes. */
      /* If OP1==3 then bounce next, conditions uncertain. */
      unsigned op1 = BITS(20,23);
      if ((op1==2 || op1 ==3) && /* OP1 */
          BITS(12,15)==0 && /* CRd */
          BITS(16,19)==0 && /* CRn */
          BITS(0,3)==0 && /* CRm */
          BITS(5,7)==1) /* OP2 */
      {
          ValidateState *state=(ValidateState *)handle;
          state->CP8_BounceNext ++;
      }
  }

  return rv;
}



static void DoASE(void *handle)
{
  ValidateState *state=(ValidateState *)handle;
  ARMulif_SetSignal(&state->coredesc,ARMSignal_SE, Signal_On);
}

static void DoAFIQ(void *handle)
{
  ValidateState *state=(ValidateState *)handle;
#ifdef VERBOSE
  printf("** DoAFIQ at corecyles:%u **\n",
         (unsigned)ARMulif_CoreCycles(&state->coredesc));
#endif
  ARMulif_SetSignal(&state->coredesc,ARMSignal_FIQ, Signal_On);
}

static void DoAIRQ(void *handle)
{
    ValidateState *state=(ValidateState *)handle;
#ifdef VERBOSE
  printf("** DoAIRQ **\n");
#endif
  ARMulif_SetSignal(&state->coredesc,ARMSignal_IRQ, Signal_On);
}

static void DoAClearReset(void *handle)
{
  ValidateState *state=(ValidateState *)handle;
    ARMulif_SetSignal(&state->coredesc,RDIPropID_ARMSignal_RESET, Signal_Off);
}

static void DoAReset(void *handle)
{
    ValidateState *state = (ValidateState *)handle;
    ARMulif_SetSignal(&state->coredesc,RDIPropID_ARMSignal_RESET, Signal_On);
    Validate_ScheduleUnretractable(
        &state->coredesc, DoAClearReset, state, 
        3 + GetCycleCount(state), 0);
}



/* CP Register Read write access for RDI */

static int CP1Read(void *handle,int type, ARMword reg,ARMword *value)
{
    ValidateState *state = (ValidateState *)handle;
 (void)type;
 *value = ValCP1Reg[reg & 0x1f];
 return ARMul_CP_DONE;
}

static int CP3Read(void *handle,int type, ARMword reg,ARMword *value)
{
    ValidateState *state = (ValidateState *)handle;
 (void)type;
 *value = ValCP3Reg[reg & 0x1f];
 return ARMul_CP_DONE;
}

static int CP4Read(void *handle,int type, ARMword reg,ARMword *value)
{
    ValidateState *state = (ValidateState *)handle;
 (void)type;
 *value = ValCP4Reg[reg & 0x1f];
 return ARMul_CP_DONE;
}

   
static int CP5Read(void *handle,int type, ARMword reg,ARMword *value)
{
    ValidateState *state = (ValidateState *)handle;
 (void)type;
 *value = state->ValCP5Reg[reg];  
 return ARMul_CP_DONE;
}

static int CP7Read(void *handle,int type, ARMword reg,ARMword *value)
{
    ValidateState *state = (ValidateState *)handle;
 (void)type;
 *value = ValCP7Reg[reg &0x1f];
 return ARMul_CP_DONE;
}
 
static int CP8Read(void *handle,int type, ARMword reg,ARMword *value)
{
  ValidateState *state=(ValidateState *)handle;
  (void)type;
  *value = ValCP8Reg[reg];  
  return ARMul_CP_DONE;
}

static int CP1Write(void *handle,int type, ARMword reg, ARMword *value)
{
  ValidateState *state = (ValidateState *)handle;
  (void)type;
  ValCP1Reg[reg] = *value; 
  return ARMul_CP_DONE;
}

static int CP3Write(void *handle,int type, ARMword reg, ARMword *value)
{
  ValidateState *state = (ValidateState *)handle;
  (void)type;
  ValCP3Reg[reg] = *value; 
  return ARMul_CP_DONE;
}

static int CP4Write(void *handle,int type, ARMword reg, ARMword *value)
{
  ValidateState *state = (ValidateState *)handle;
  (void)type;
  ValCP4Reg[reg] = *value; 
  return ARMul_CP_DONE;
}

static int CP5Write(void *handle,int type, ARMword reg,ARMword *value)
{
  ValidateState *state = (ValidateState *)handle;
  (void)type;
  state->ValCP5Reg[reg] = *value; 
  return 1;
}

static int CP7Write(void *handle,int type, ARMword reg, ARMword *value)
{
  ValidateState *state=(ValidateState *)handle;
  (void)type;
  ValCP7Reg[reg] = *value;
  return 1;
}

static int CP8Write(void *handle,int type, ARMword reg,ARMword *value)
{
  ValidateState *state=(ValidateState *)handle;
  (void)type;
  ValCP8Reg[reg] = *value;
  return 1;
}

static unsigned int const RegBytes[17] = {16, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4};
  
IMPLEMENT_COPRO_DESC_FN_FROM_ARRAY(ValCPDesc, ValidateState, RegBytes)

/* Register CP0 co-processor */
ARMul_CoprocessorV5 CP0_cp = {CP0CDP, 
                              CP0LDCMCR /*MCR*/, CP0STCMRC /* MRC */,
                              NULL, NULL, /* MCRR, MRRC */
                              CP0LDCMCR /* LDC */, CP0STCMRC /* STC */,
                              NULL /* CP0_Desc */,
                              NULL /* ReadReg */, NULL /* WriteReg */} ;

/* Register CP1 co-processor */
static ARMul_CoprocessorV5 CP1_cp = {CP1CDP, 
                              CP1MCR /*MCR*/, CP1MRC /* MRC */,
                              CP1MCRR,CP1MRRC, /* MCRR, MRRC */
                              CP1LDC /* LDC */, CP1STC /* STC */,
                              ValCPDesc /* Desc */,
                              CP1Read, CP1Write};

/* Register CP2 co-processor */
ARMul_CoprocessorV5 CP2_cp = {CP2CDP, 
                              CP2LDCMCR /*MCR*/, CP2STCMRC /* MRC */,
                              NULL, NULL, /* MCRR, MRRC */
                              CP2LDCMCR /* LDC */, CP2STCMRC /* STC */,
                              NULL /* CP2_Desc */,
                              NULL /* ReadReg */, NULL /* WriteReg */} ;

/* Register CP3 co-processor */
static ARMul_CoprocessorV5 CP3_cp = {CP3CDP, 
                              CP3MCR /*MCR*/, CP3MRC /* MRC */,
                              CP3MCRR,CP3MRRC, /* MCRR, MRRC */
                              CP3LDC /* LDC */, CP3STC /* STC */,
                              ValCPDesc /* Desc */,
                              CP3Read, CP3Write};


/* Register CP4 co-processor */
static ARMul_CoprocessorV5 CP4_cp = {CP4CDP, 
                              CP4MCR /*MCR*/, CP4MRC /* MRC */,
                              CP4MCRR,CP4MRRC, /* MCRR, MRRC */
                              CP4LDC /* LDC */, CP4STC /* STC */,
                              ValCPDesc /* Desc */,
                              CP4Read, CP4Write};



/* Register CP5 co-processor */
static ARMul_CoprocessorV5 CP5_cp = {CP5CDP, 
                              CP5MCR /*MCR*/, CP5MRC /* MRC */,
                              CP5MCRR, CP5MRRC, /* MCRR, MRRC */
                              CP5LDC /* LDC */, CP5STC /* STC */,
                              ValCPDesc /* Desc */,
                              CP5Read, CP5Write};

/* Register CP7 co-processor */
static ARMul_CoprocessorV5 CP7_cp = {CP7CDP, 
                              CP7MCR /*MCR*/, CP7MRC /* MRC */,
                              CP7MCRR,CP7MRRC, /* MCRR, MRRC */
                              CP7LDC /* LDC */, CP7STC /* STC */,
                              ValCPDesc /* Desc */,
                              CP7Read, CP7Write};
/* Register CP8 co-processor */
static ARMul_CoprocessorV5 CP8_cp = {CP8CDP, 
                              CP8MCR /*MCR*/, CP8MRC /* MRC */,
                              CP8MCRR,CP8MRRC, /* MCRR, MRRC */
                              CP8LDC /* LDC */, CP8STC /* STC */,
                              ValCPDesc /* Desc */,
                              CP8Read, CP8Write};


/* Validation suite co-processor model */

#include <time.h>
#include <errno.h>
#include <string.h>
#include "rdi_hif.h"


/*
 * install ourselves as a Coprocessor, without claiming to be an OS model
 */
static ARMul_Error CPInit(ValidateState *state,
                          toolconf config)
{
    ARMul_Error err = RDIError_NoError;

    Hostif_PrettyPrint(state->hostif, config, ", ARM Validation system");


  state->vs_CoproIFType = ToolConf_DLookupUInt(
      config,ARMulCnf_CoprocessorInterfaceType, 7);
  state->ValCP5_LDCL_Words = ToolConf_DLookupUInt(
        config, (tag_t)"CP5_LDCL_WORDS",2);

  state->bARM9_CoproIF = ToolConf_DLookupBool(
      config, (tag_t)"ARM9COPROCESSORINTERFACE", BOOLIFY((state->vs_CoproIFType == 9)));

  state->vcp_InterfaceDelay = state->bARM9_CoproIF ? 3 : 0;

  state->bARM9_Extensions = ToolConf_DLookupBool(
      config, (tag_t)"ARM9EXTENSIONS", FALSE);

    {
        Hostif_PrettyPrint(state->hostif, config,
                           ", System cycle event scheduling");
    }
    if (ToolConf_DLookupBool(config,(tag_t)"CP0",FALSE))
    {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 0, &CP0_cp, state);
    }
    if (!err && ToolConf_DLookupBool(config,(tag_t)"CP1",FALSE)) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 1, &CP1_cp, state);
    }
    if (!err && ToolConf_DLookupBool(config,(tag_t)"CP2",FALSE)) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 2, &CP2_cp, state);
    }
    if (!err && ToolConf_DLookupBool(config,(tag_t)"CP3",FALSE)) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 3, &CP3_cp, state);
    }
    if (!err) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 4, &CP4_cp, state);
    }
    if (!err) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 5, &CP5_cp, state);
    }
    if (!err) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 7, &CP7_cp, state);
    }
    if (!err) {
        err = ARMulif_InstallCoprocessorV5(
            &state->coredesc, 8, &CP8_cp, state);
    }

    return err;
}



/*--------------- RDI STUFF ------------- */

BEGIN_INIT(Validate)
    if (coldboot)
    { int err = CPInit(state, config);
      if (err) return err;
      assert(state->coredesc.rdi != NULL);
    }
END_INIT(Validate)

BEGIN_EXIT(Validate)
END_EXIT(Validate)

/*-------------- endof RDI stuff ----------------*/



#define SORDI_DLL_DESCRIPTION_STRING "Validation Coprocessors"
#define SORDI_RDI_PROCVEC Validate_AgentRDI
#include "perip_sordi.h"

#include "perip_rdi_agent.h"
    IMPLEMENT_AGENT_PROCS_NOEXE_NOMODULE(Validate)
    IMPLEMENT_AGENT_PROCVEC_NOEXE(Validate)



/* EOF validate.c */