tmgrem.h

realview22.rar

#define PINFLG_1_0      0x01    /* 0/1 values only */
#define PINFLG_MSTATE   0x02    /* multi-state */
#define PINFLG_ANALOG   0x03    /* analog */
#define PINFLG_INT      0x04    /* write to it from external causes int */
#define PINFLG_RO       0x10    /* read-only (from CPU) */
#define PINFLG_WO       0x20    /* write-only (from CPU) */
#define PINFLG_INTID    0xFFF0  /* interrupt ID shifted left 8 */

  /* PINACC_REQ indicates what action is expected of 
     _SimAccessPins. In particular is read vs. write and
     debug (no side effect) and active (side effecting).
     Note that both calls may be made when running or
     stopped. This means that stopped-time calls should
     pend the effect if any (such as an interrupt). */
typedef enum 
{
  PINACC_R_DEBUG,               /* read for debug (no effect) */
  PINACC_W_DEBUG,               /* write for debug (no side-effect) */
  PINACC_R_ACTIVE,              /* read and cause side-effects */
  PINACC_W_ACTIVE               /* write and cause side-effects */
} PINACC_REQ;

  /* MEMACC_TYPE is used in a callback to indicate the memory action
     taking place. Only Read and Write are needed. If the simulator has
     more information, it can use the others. Fetch and Vector provide
     information about why an access is taking place. Io and Extern are
     masks to OR onto a value to indicate details - I/O memory operation
     and/or external memory operation. These latter two are only used
     when page and address is not enough to know that. For example, if
     the processor supports an explicit external memory operation where
     the external memory overlaps the address of internal memory, the
     Extern mask should be used. If an IO operation does not use the
     normal memory bus or uses special memory handling (clock stopping
     for example) and the page is not a factor, this mask should be set */
typedef enum
{
  MEMACC_READ,                  /* memory is being read */
  MEMACC_WRITE,                 /* memory is being written */
  MEMACC_FETCH,                 /* pipeline load of code */
  MEMACC_VECTOR,                /* interrupt load */
  MEMACC_DMA,                   /* DMA access */
  MEMACC_IO=0x40,               /* I/O access if page is not enough */
  MEMACC_EXTERN=0x80            /* mask if external memory access */
} MEMACC_TYPE;

  /* now trace buffer types. These go with raw data only when TRCFLG_DEEP
     is set. This is requested via REMTRC_TYPES and is paired to MINBUF.
     The buff_extra field contains the types + stall value (if any) above
     it, and the value (if any).                                        */
typedef enum
{
  TRC_READ=MEMACC_READ,         /* address of read */
  TRC_WRITE=MEMACC_WRITE,       /* address of write */
  TRC_FETCH=MEMACC_FETCH,       /* address of pipeline load of code */
  TRC_VECTOR=MEMACC_VECTOR,     /* address interrupt load (vector) */
  TRC_DMA=MEMACC_DMA,           /* address of DMA access */
  TRC_INSTR=0x08                /* address of execute instruction */
} TRC_TYPE;
#define TRC_TYPE        UINT8
#define TRC_TYPE_MASK   0x0F    /* mask of types */
#define TRC_DISC        0x10    /* discontinuity from trace off */
#define TRC_VALUE       0x20    /* data value (paired with address) */
#define TRC_STALL       0x40    /* stall cause+value above this type */
  /* remaining data in upper word of buff_extra with type */
#define TRC_GET_SZ(extra)       ((extra>>8)&0xF) /* size as ANDAT_xxx */
#define TRC_SET_SZ(sz)          (sz<<8)
#define TRC_GET_STALLCAUSE(extra) (extra>>28)   /* 0-0xE */
#define TRC_SET_STALLCAUSE(cause) (cause<<28)
#define TRC_GET_STALL(extra)    ((extra>>12)&0x0FFF) /* time lost */
#define TRC_SET_STALL(stall)    (stall<<12)

  /* STEP_SIT indicates the STEP situation when a STEP callback is made.
     Only the STEP one is needed. The others are used when the simulator
     can provide finer granularity.                                     */
typedef enum
{
  STPSIT_STEP,                  /* normal instruction step */
  STPSIT_PIPELOAD,              /* pipeline reload after branch */
  STPSIT_VECTOR,                /* interrupt vectoring operation */
  STPSIT_PARTIAL                /* partial step for pipeline */
} STEP_SIT;

  /* STALL_CAUSE is used by the stall callback. It indicates a general
     reason for a stall. It allows the user to home in on problems in
     their code due to poor choice of instructions groups or misuse of
     memory. Since DSPs use various techniques for getting maximal
     performance (dual-access/dual-port memory, multiple busses, tree
     ALU for super scalar operations, half-clock bus operations, and
     so on), it is useful to be able to see when a program is not 
     optimal. This mechanism allows ASPEX to show where they are running
     less than optimally and to cost it according to use (loops for
     example). This also allows an overhead computation to be done. */
typedef enum
{
  STALL_WR,                     /* write then read in same memory */
  STALL_RW,                     /* read then write in same memory */
  STALL_RR,                     /* two reads in single access memory */
  STALL_WW,                     /* two writes in single access memory */
  STALL_RES,                    /* resource locked (such as ALU) */
  STALL_WS,                     /* memory hit */
  STALL_BRA,                    /* branch reload */
  STALL_DMA,                    /* DMA access */
  STALL_CACHE_MISS,             /* cache miss */
  STALL_CACHE_OTHER,            /* other cache costs (reload, etc) */
  STALL_PAGE_VAL,               /* page validate */
  STALL_OTHER=128               /* other causes */
} STALL_CAUSE;

  /* CMD_FILLIN is the same as that defined in tmgcmd.h as the CMD_INFO
     block structure. This is a stub only. If commands and lists are
     supported, you must also include tmgcmd.h.                 */
typedef struct _CMD_FILLIN CMD_FILLIN;
#define LIST_PIPELINE   0x8000  /* pipeline list for cycle-acc sims */
#define LIST_PIPEDETAIL 0x8001  /* pipeline detail string (msg) */
#define LIST_STALL_ANA  0x8002  /* stall list (statistical) */
#define LIST_CACHE_ANA  0x8003  /* cache list (statistical) */
#define LIST_PROPERTIES 0x8100  /* list of properties supported */

  /* SAVEREST_REQ indicates the _SimSaveRestore action
     requested. The exaxct meaning of minimal save or restore
     vs. all is up to the simulator.                    */
typedef enum
{
  SREST_SAVE_ALL,               /* save memory and all regs */
  SREST_SAVE_MIN,               /* minimal save - regs only */
  SREST_REST_ALL,               /* restore what was saved */
  SREST_REST_MIN                /* restore minimal */
} SAVEREST_REQ;

  /* ENAMEM_REQ is used to indicate what action to take in
     _SimEnableMemRegCallback. The memory enable allows for
     enabling/disabling a range of memory (or just a page if 
     the SIMCBF_ENA_PAGE flag was set). The register enable
     allows for selective callbacks on register changes or
     accesses. Note that the default is all memory is enabled
     and all registers are disabled. The registers are indicated
     using page=REG_PAGE and address=reg-id. The range will be
     used to select a set of registers in range.        */
typedef enum
{
  ENAMEM_CLEAR,                 /* clear all (all mem ena, all reg dis) */
  ENAMEM_ADD_MEM,               /* add memory range (or page) */
  ENAMEM_DEL_MEM,               /* remove memory range (or page) */
  ENAMEM_ADD_REG,               /* add register (or range) */
  ENAMEM_DEL_REG                /* remove register (or range) */
} ENAMEM_REQ;

#define REG_PAGE        0xFFFFFFFF /* register page */

typedef enum {SSTATE_NORMAL, SSTATE_IDLE, SSTATE_RESET} SIM_STATE;
#define SIM_STATE UINT8

struct SIM_EXTENSION_INFO
{
  Boolean       name_valid;
  Boolean       full_id_valid;
  Boolean       clock_valid;
  Boolean       context_valid;
  Boolean       reg_ext_valid;
  Boolean       state_valid;
  Boolean       endian_valid;
  Boolean       pad3;
  UINT16        num_props;      /* number of properties */
  UINT16        num_pins_valid;
  UINT16        pad4, pad5;
  char          *name;          /* name to use for showing to user (in
                                   name\ndescription format)    */
  char          *full_id;       /* ID in RV-msg format (name\nmodules...) */
  UINT32        clock;          /* clock in MHz*100 (so, 2.1MHz=210) */
  char          *context;       /* context name if not NULL context */
  char          **prop;         /* properties to set/get */
  char          **pins;         /* x=2 type array (meaning up to sim) */
  UINT32        reg_ext_cseq;   /* one bit for each bank supported by seq */
  SIM_STATE     state;          /* state at start or request to change */
  UINT8         is_big;         /* True if big-endian, else little */
  UINT8         pad7, pad8;
  UINT32        pad9, pad10, pad11, pad12;
};

  /* now define flags for code sequence support */
#ifndef TABSRSRET_MODE
#define TABSRSRET_MODE        0x000F     /* processor mode to operate under */
#define TABSRSRET_TYPE        0x0070     /* type of "operation" this seq is */
#define   TABSRSTYPE_UNK        0x00       /* unknown */
#define   TABSRSTYPE_COPROC     0x10       /* co-processor */
#define   TABSRSTYPE_COPROC_MEM 0x20       /* co-processor */
#define   TABSRSTYPE_JTAG       0x30       /* JTAG */
#define   TABSRSTYPE_MEM        0x40       /* memory */
#define   TABSRSTYPE_MON        0x50       /* monitor extension */
#define TABSRSRET_ISET        0x0180     /* instruction set used by code squence: processor-defined */
#define TABSRSRET_EXTRA       0x0000FE00 /* extra processsor-specific bits */
#define TABSRSSHIFT_EXTRA     9
#define TABSRSRET_NUMREGS     0x00030000 /* number of registers affected (usually 1) */
#define TABSRSSHIFT_NUMREGS   16
#define TABSRSRET_REGOFF      0x000C0000 /* offset of specified register in NUMREGs */
#define TABSRSSHIFT_REGOFF    18
#define TABSRSRET_REGDIRTY    0x00F00000 /* number of core regs trashed by operation */
#define TABSRSSHIFT_REGDIRTY  20
#define TABSRSRET_N_RESULTS   0xFF000000 /* mask of core registers with results */
#define TABSRSSHIFT_N_RESULTS 24
#endif

#endif