runfast.s
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AREA RunFast, CODE, READONLY
VFPEnable EQU 0x40000000
RF_Enable EQU 2_11:SHL:24
; Bit pattern to enable RunFast mode
; FPSCR [24] - Flush to Zero mode
; FPSCR [25] - Default NaN mode
CM_BASE EQU 0x10000000
CM_INIT EQU 0x24
CM_LOCK EQU 0x14
CM_LOCK_VALUE EQU 0xA05F
VFPTST EQU 2_11:SHL:12
EXPORT RunFast_Enable
RunFast_Enable FUNCTION
MOV r0,#RF_Enable
FMXR FPSCR, r0 ; FPSCR = r0
BX LR
ENDFUNC
IF :DEF: INIT_CM10rev0_VFP
EXPORT CM_VFP_enable
CM_VFP_enable FUNCTION
; enable Integrator Core Module to allow use of VFP
MOV r0, #CM_BASE ; set r0 to base address of core module
; register space
LDR r2, =CM_LOCK_VALUE
STR r2,[r0,#CM_LOCK] ; unlock CM_INIT
LDR r1, [r0,#CM_INIT]
BIC r1, r1,#VFPTST ; clear bits 12 and 13
STR r1, [r0,#CM_INIT] ; of CM_INIT
MOV r2,#0
STR r2,[r0,#CM_LOCK] ; lock CM_INIT
BX LR
ENDFUNC
ENDIF
EXPORT Enable_VFP
Enable_VFP FUNCTION
if "6" <={ARCHITECTURE}
MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register
ORR r1, r1, #(0xf << 20) ; enable full access for p10,11
MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1
MOV r1, #0
MCR p15, 0, r1, c7, c5, 4 ; flush prefetch buffer because of FMXR below and
; CP 10 & 11 were only just enabled
endif
; Enable VFP itself
MOV r0,#VFPEnable
FMXR FPEXC, r0 ; FPEXC = r0
BX LR
ENDFUNC
END
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