vfpwrapper.s

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;;; vfpwrapper.s
;;; VFP_Computation_Engine_Wrapper
;;; The point returned to in the application, after the
;;; VFP_UNDEF_handler has prepared a bounce description controlbuffer.
;;; Copyright (C) ARM Limited, 2002. All rights reserved.

        IMPORT __rt_memcpy_w

VFP_Computation_Description_Size EQU 136

        GET controlbuffer_h.s

        IMPORT _VFP_Computation_Engine

        GBLL ARCH_V6_OR_LATER
  if "6" <= {ARCHITECTURE} ; ok until architecture 10
ARCH_V6_OR_LATER SETL {TRUE}
  else
ARCH_V6_OR_LATER SETL {FALSE}
  endif

        AREA |.text.wrapper|, CODE, READONLY

        PRESERVE8

VFP_Computation_Engine_Wrapper PROC
        EXPORT VFP_Computation_Engine_Wrapper

;;; On entry all registers live
;;; return address saved in thread-local control buffer
;;; r14 contains VFP_Computation_Description pointer

  if ARCH_V6_OR_LATER
;;; Reserve space for saved CPSR, return address and saved R14
        SUB sp, sp, #12
        FRAME PUSH 4
        FRAME PUSH {r14} ; frame assumes return address in r14
        FRAME PUSH 4
  else
;;; Reserve space for return address and saved R14
        SUB sp, sp, #8
        FRAME PUSH {r14} ; frame assumes return address in r14
        FRAME PUSH 4
  endif

;;; Push other callee-save registers and also r4-r5
        STMFD sp!, {r0-r5,r12}
        FRAME PUSH 7*4 ; assembler supports only ATPCS saves

;;; Copy frame pointer to r5, then force 8-byte stack alignment
;;; (whether or not the stack was aligned when the bounce was taken)
        MOV r5, sp
        BIC sp, sp, #7

;;; Allocate space on stack for a copy of the Computation Description
        SUB sp, sp, #VFP_Computation_Description_Size

;;; Thread-local control buffer address is in R14

;;; Copy saved PSR to r4, and return address to top of stack frame
        LDMIA r14,{r1,r4,r12} ; R1=PC, R4=PSR, R12=R14
        STR r12, [r5, #(7 * 4)]
        STR r1, [r5, #(8 * 4)]

;;; Make a copy of the computation description on the stack,
;;; to support recursive calls due to bounces in user trap handlers
        MOV r2, #VFP_Computation_Description_Size
        ADD r1, r14, #ControlBuffer_Data_Offset
        MOV r0, sp  ; address of computation description on stack
        BL __rt_memcpy_w ; word aligned memcpy, returns void

;;; Process the VFP bounce
        MOV r0, sp  ; address of computation description on stack
        BL _VFP_Computation_Engine

;;; Return: restore PSR, restore registers and return

  if ARCH_V6_OR_LATER
        MOV sp, r5 ; restore stack pointer to saved regs location
        STR r4, [sp,#9*4] ; copy saved PSR to register dump
        LDMFD sp!, {r0-r5,r12,r14}
        FRAME POP 8*4
        RFEFD sp! ; this restores the saved E bit as well as saved flags
        FRAME POP {pc}
        FRAME POP 4
  else
;;; The PSR can be restored in this way only because we know we are
;;; returning to ARM state.
        MSR CPSR_sf, r4

        MOV sp, r5 ; restore stack pointer to saved regs location
        LDMFD sp!, {r0-r5,r12,r14,pc}
        FRAME POP 8*4
        FRAME POP {pc}
  endif

        ENDP

        END
;;; end of file vfpwrapper.s