initmpmc.s

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;;  Copyright ARM Ltd 2004. All rights reserved.
;;
;;  This code initializes the SDRAM on the Versatile platform.
        
        AREA InitMPMC, CODE, READONLY

        EXPORT InitMPMCentry
        
; Mpmc Dynamic Memory Config
; --------------------------

MPMC_Base               EQU 0x10110000
MPMC_Base_Plus_256      EQU 0x10110100
MPMC_Base_Plus_1024     EQU 0x10110400
MPMC_Base_Plus_1152     EQU 0x10110480

MPMCControl             EQU 0x10110000
MPMCStatus              EQU 0x10110004
MPMCConfig              EQU 0x10110008
MPMCDynamicControl      EQU 0x10110020
MPMCDynamicRefresh      EQU 0x10110024
MPMCDynamicReadConfig   EQU 0x10110028
MPMCDynamictRP          EQU 0x10110030
MPMCDynamictRAS         EQU 0x10110034
MPMCDynamictSREX        EQU 0x10110038
MPMCDynamictWR          EQU 0x10110044
MPMCDynamictRC          EQU 0x10110048
MPMCDynamictRFC         EQU 0x1011004c
MPMCDynamictXSR         EQU 0x10110050
MPMCDynamictRRD         EQU 0x10110054
MPMCDynamictMRD         EQU 0x10110058
MPMCDynamictCDLR        EQU 0x1011005c
MPMCStaticExtendedWait  EQU 0x10110080
MPMCDynamicConfig0      EQU 0x10110100
MPMCDynamicRasCas0      EQU 0x10110104
MPMCDynamicConfig1      EQU 0x10110120
MPMCDynamicRasCas1      EQU 0x10110124
MPMCDynamicConfig2      EQU 0x10110140
MPMCDynamicRasCas2      EQU 0x10110144
MPMCDynamicConfig3      EQU 0x10110160
MPMCDynamicRasCas3      EQU 0x10110164
MPMCAHBTimeout0         EQU 0x10110408
MPMCAHBTimeout1         EQU 0x10110428
MPMCAHBTimeout2         EQU 0x10110448  
MPMCAHBTimeout3         EQU 0x10110468
MPMCAHBTimeout4         EQU 0x10110488
MPMCAHBTimeout5         EQU 0x101104a8

; Define constants
; ----------------

ModeRegAddr             EQU 0x20000       ; Define Mode Register address, used when reading from rams
SDRAMUpperAddrLimit     EQU 0x04000000    ; Define upper limit of SDRAM
SDRAMReadWriteLoc       EQU 0x00000160    ; Define SDRAM location to perform Data Bus checks at (should be 32-bit wide databus)

SRAMBank0AddrLimit      EQU 0x00040000    ; Bank 0 is only 512K
SRAMUpperAddrLimit      EQU 0x04000000    ; Banks (1-3) are 16M
SRAMReadWriteLoc        EQU 0x30000000    ; Define SRAM location to perform Data Bus checks at (should be 32-bit wide databus)

SRAMBank0BaseAddr       EQU 0x30000000    ; Define SRAM Bank 0 base addr
SRAMBank1BaseAddr       EQU 0x34000000    ; Define SRAM Bank 1 base addr
SRAMBank2BaseAddr       EQU 0x38000000    ; Define SRAM Bank 2 base addr
SRAMBank3BaseAddr       EQU 0x3C000000    ; Define SRAM Bank 3 base addr

SDRAMBank4BaseAddr      EQU 0x00000000                          ; Define SDRAM Bank 4 base addr
SDRAMBank4BaseAddrMod   EQU 0x04000000                          ; Define SDRAM Bank 4 base addr
SDRAM4ModeRegAddr       EQU SDRAMBank4BaseAddrMod + ModeRegAddr ; Define SDRAM Bank 4 mode register addr

SDRAMBank5BaseAddr      EQU 0x08000000                          ; Define SDRAM Bank 5 base addr
SDRAM5ModeRegAddr       EQU SDRAMBank5BaseAddr + ModeRegAddr    ; Define SDRAM Bank 5 mode register addr

SDRAMBank6BaseAddr      EQU 0x70000000                          ; Define SDRAM Bank 6 base addr
SDRAM6ModeRegAddr       EQU SDRAMBank6BaseAddr + ModeRegAddr    ; Define SDRAM Bank 6 mode register addr

SDRAMBank7BaseAddr      EQU 0x78000000                          ; Define SDRAM Bank 7 base addr
SDRAM7ModeRegAddr       EQU SDRAMBank7BaseAddr + ModeRegAddr    ; Define SDRAM Bank 7 mode register addr

; -----------------------------------------------------------------------------

SC_BASE         EQU 0x101E0000
SC_CTRL         EQU 0x00
SC_REMAP_STAT   EQU 0x200

; -----------------------------------------------------------------------------

; Initialisation sequence
; -----------------------

InitMPMCentry

        LDR     r6, =MPMCConfig 
        MOV     r0, #0x0

        ; Set endian bit
        STR     r0, [r6]

        LDR     r6, =SC_BASE
        LDR     r7, [r6, #SC_CTRL]

        LDR     r0, =SC_REMAP_STAT
        TST     r7, r0                        ; Check Remap Status
        BNE     __platform_mpmc_init_start

        MOV     pc, lr


__platform_mpmc_init_start
        LDR     r6, =MPMC_Base

; Set AHB Timeouts
; -----------------------------------------------------------------------------
        LDR     r7, =MPMC_Base_Plus_1024

        MOV     r0, #0x2
        STR     r0, [r7, #MPMCAHBTimeout0 - MPMC_Base_Plus_1024]

        MOV     r0, #0x0
        STR     r0, [r7, #MPMCAHBTimeout1 - MPMC_Base_Plus_1024]
        STR     r0, [r7, #MPMCAHBTimeout2 - MPMC_Base_Plus_1024]
        STR     r0, [r7, #MPMCAHBTimeout3 - MPMC_Base_Plus_1024]
        ADD     r7, r7, #0x80
        STR     r0, [r7, #MPMCAHBTimeout4 - MPMC_Base_Plus_1152]
        STR     r0, [r7, #MPMCAHBTimeout5 - MPMC_Base_Plus_1152]

; Set Clocking scheme
; -----------------------------------------------------------------------------
        MOV     r0, #0xFF
        ADD     r0, r0, #0x12
        STR     r0, [r6, #MPMCDynamicReadConfig - MPMC_Base]

; Set SDRAM Initialisation Value (I) to NOP (MPMCDynamicControl [8:7] to 2'b11)
; -----------------------------------------------------------------------------

        ADD     r7, r6, #1
        ADDS    r7, r7, #0xFF           ; MPMC_Base_Plus_256
        
        MOV     r0, #0xC
        MOVS    r0, r0, LSL #12
        ADDS    r0, r0, #0xFF
        ADDS    r0, r0, #0x84           ; 0xC183

        STR     r0, [r6, #MPMCDynamicControl - MPMC_Base]

; Set SDRAM Initialisation Value (I) to PALL (MPMCDynamicControl [8:7] to 2'b10)
; -----------------------------------------------------------------------------

        SUBS    r0, r0, #0x80           ; 0xC103
        STR     r0, [r6, #MPMCDynamicControl - MPMC_Base]


; Write a small value (1) into the refresh register (MPMCDynamicRefresh)
; -----------------------------------------------------------------------------

; 0x1 (x16) = 16 cycles between refreshes

        MOV     r0, #1
        STR     r0, [r6, #MPMCDynamicRefresh - MPMC_Base]

; Perform refresh cycles
; -----------------------------------------------------------------------------

        MOV     r0, #0x10   ; Set required number of loop cycles to allow enough refreshes
1       SUBS    r0, r0, #1
        BNE     %b1

; Write operational value into refresh reg (MPMCDynamicRefresh)
; -----------------------------------------------------------------------------

; For 16us refresh rate, with 60MHz clock = (16 * 60)/16 = 10

        MOV     r0, #0x3C
        STR     r0, [r6, #MPMCDynamicRefresh - MPMC_Base]

; Program RAS/CAS latency (MPMCDynamicRASCAS[0,1,2,3])
; -----------------------------------------------------------------------------

; MPMCDynamicRASCASn [10:7] -> CAS latency in half cycle increments
; MPMCDynamicRASCASn  [3:0] -> RAS latency in one cycle increments
; 32'h0000 0202 => RAS = 2 cycles, CAS = 2 cycles
; 32'h0000 0182 => RAS = 2 cycles, CAS = 1.5 cycles

        MOV     r0, #0xFF
        ADDS    r0, r0, #0x83           ; 0x182
        ADDS    r0, r0, #0x80           ; 0x202
        STR     r0, [r7, #MPMCDynamicRasCas0 - MPMC_Base_Plus_256]
        STR     r0, [r7, #MPMCDynamicRasCas1 - MPMC_Base_Plus_256]
        STR     r0, [r7, #MPMCDynamicRasCas2 - MPMC_Base_Plus_256]
        STR     r0, [r7, #MPMCDynamicRasCas3 - MPMC_Base_Plus_256]

; Write operational value into Config reg (MpmcDynamicConfig n)
; -----------------------------------------------------------------------------

; For RBC : 32'h 0000 4880
; For BRC : 32'h 0000 5880

        MOV     r0, #0xB1
        MOVS    r0, r0, LSL #7              ; 0x5880
        STR     r0, [r7, #MPMCDynamicConfig0 - MPMC_Base_Plus_256]
        STR     r0, [r7, #MPMCDynamicConfig1 - MPMC_Base_Plus_256]
        STR     r0, [r7, #MPMCDynamicConfig2 - MPMC_Base_Plus_256]
        STR     r0, [r7, #MPMCDynamicConfig3 - MPMC_Base_Plus_256]


; Set DynamicRP Register
; -----------------------------------------------------------------------------
        MOV     r0, #0x2
        STR     r0, [r6, #MPMCDynamictRP - MPMC_Base]

; Set DynamicRAS Register
; -----------------------------------------------------------------------------
        MOV     r0, #0x3
        STR     r0, [r6, #MPMCDynamictRAS - MPMC_Base]

; Set DynamicSREX Register
; -----------------------------------------------------------------------------
        MOV     r0, #0x5
        STR     r0, [r6, #MPMCDynamictSREX - MPMC_Base]
        MOV     r1, #0x4

; Set DynamicWR Register
; -----------------------------------------------------------------------------
        STR     r1, [r6, #MPMCDynamictWR - MPMC_Base]
; Set DynamicRC Register
; -----------------------------------------------------------------------------
        STR     r0, [r6, #MPMCDynamictRC - MPMC_Base]
; Set DynamicRFC Register
; -----------------------------------------------------------------------------
        STR     r0, [r6, #MPMCDynamictRFC - MPMC_Base]
; Set DynamicXSR Register
; -----------------------------------------------------------------------------
        STR     r0, [r6, #MPMCDynamictXSR - MPMC_Base]

; Set DynamicRRD Register
; -----------------------------------------------------------------------------
        MOV     r0, #1
        STR     r0, [r6, #MPMCDynamictRRD - MPMC_Base]

; Set DynamicMRD Register
; -----------------------------------------------------------------------------
        MOV     r1, #2
        STR     r1, [r6, #MPMCDynamictMRD - MPMC_Base]

; Set DynamicCDLR Register
; -----------------------------------------------------------------------------
        STR     r0, [r6, #MPMCDynamictCDLR - MPMC_Base]


; Set SDRAM Initialisation Value (I) to MODE (MPMCDynamicControl [8:7] to 2'b01)
; -----------------------------------------------------------------------------

        MOV     r0, #0x83
        STR     r0, [r6, #MPMCDynamicControl - MPMC_Base]

; Program the Mode Registers. SDRAM Addr[5] = 1'b1, all others 0
; -----------------------------------------------------------------------------

; SDRAM Addr[11:0] = 12'h020
; For RBC : SDRAM Addr[11:0] translates to HADDR [25:13] = 0x40000
; For BRC : SDRAM Addr[11:0] translates to HADDR [23:11] = 0x10000
; To program the register, do a read from the memory base addr + the value above

        LDR     r5, =SDRAM4ModeRegAddr
        LDR     r0, [r5]

        LDR     r5, =SDRAM5ModeRegAddr
        LDR     r0, [r5]

        LDR     r5, =SDRAM6ModeRegAddr
        LDR     r0, [r5]

        LDR     r5, =SDRAM7ModeRegAddr
        LDR     r0, [r5]
;

; Set SDRAM Initialisation Value (I) to PALL
; -----------------------------------------------------------------------------

        MOV     r0, #0x83
        ADD     r0, r0, #0x80
        STR     r0, [r6, #MPMCDynamicControl - MPMC_Base]


; Set SDRAM Initialisation Value (I) to NORMAL (MPMCDynamicControl [8:7] to 2'b00)
; -----------------------------------------------------------------------------

        MOV     r0, #3
        STR     r0, [r6, #MPMCDynamicControl - MPMC_Base]


; Mpmc Dynamic Memory Config complete
; -----------------------------------------------------------------------------

        MOV     pc, lr

; -----------------------------------------------------------------------------

        END

; end of file mpmc_init.s