📄 clock_irq.c
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/*
** Copyright (C) ARM Limited, 2002. All rights reserved.
*/
/* clock_irq.c */
/*
** This implements a simple clocking mechanism on the Integrator platform
**
** It reads from the Real Time Clock that is present on the
** Integrator AP.
**
** This clock has a resolution of 1 second, so a large number of Dhrystone
** iterations are necessary for reliable results.
** The initialization code sets this clock to zero.
*/
/*
** Define SCATTER_PERIP if the clock register locations are
** defined in a scatter file
*/
static volatile int clock_counter;
#ifdef SCATTER_PERIP
#include "intgrt_struct.h"
extern struct cm cm0;
extern struct irq irq0;
extern struct timer timer1;
#define CM_REFCT cm0.refct
#define IRQEnableClear irq0.EnableClear
#define IRQEnableSet irq0.EnableSet
#define Timer1Load timer1.Load
#define Timer1Value timer1.Value
#define Timer1Control timer1.Control
#define Timer1Clear timer1.Clear
#else
#include "intgrt.h"
#endif
/* Return the current clock value */
/* In order to obtain a high precision, whilst keeping the performance */
/* penalty low, IRQs are only occuring at a rate of 100 per second, but */
/* the current timer value is factored in. */
unsigned ref_clock(void)
{
int clk, count;
clk=clock_counter;
count=Timer1Value;
if (clk==clock_counter) // A timer IRQ did not occur between the counter and timer values being read.
{
return clk*15000+(15000-count);
}
else // A timer IRQ did occur between the counter and timer values being read
{
return (clk+1)*15000;
}
}
void init_clock(void)
{
clock_counter = 0;
Timer1Load = 15000; // With /16, sets 1/100 seconds.
Timer1Control = 0xC4; // Periodic mode, Divide by 16, enabled.
IRQEnableClear = 0x003FFFFF; // Disable all interrupts in IRQ controller.
IRQEnableSet = 0x40; // Enable Timer1 IRQ (IRQs should still be disabled in the core.
}
__irq void inc_clock(void)
{
Timer1Clear = 0; // Clear the interrupt
clock_counter++; // And increment our 1/100 second clock.
}
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