cm926ejs.bcd

realview22.rar

# CM926EJS.BCD file. This file contains the board definition for the
# ARM926EJ-S Core Module
#
# Copyright 2001-2003 ARM Limited.

[BOARD=CM926EJ-S] 
Advanced_Information.ARM926EJ-S={\
  Memory_block.M_CM_Regs={\
    start=0x10000000:length=0x800000:description="CM Registers"\
  }:Memory_block.M_CM_ROM={\
    start=0x0000:length=0x100000:access=ROM:description="Boot"\
  }:Memory_block.M_CM_SDRAM={\
    start=0x100000:length=0xFF00000:access=RAM:description="SDRAM"\
  }:Memory_block.M_CM_SSRAM={\
    start=0x0000:length=0x100000:description="SSRAM"\
  }:Map_rule.R_MBDET={\
    register=G_CM_CTRL:mask=0x0002:value=0x0002:on_equal=M_CM_SSRAM:\
        on_equal=M_CM_SDRAM\
  }:Map_rule.R_NMBDET_REMAP={\
    register=G_CM_CTRL:mask=0x0006:value=0x0004:on_equal=M_CM_SSRAM:\
        on_equal=M_CM_SDRAM\
  }:Map_rule.R_NMBDET_NREMAP={\
    register=G_CM_CTRL:mask=0x0006:value=0x0000:on_equal=M_CM_ROM:on_equal=M_CM_SDRAM\
  }:Register_enum.E_ENABLE={\
    names="Disabled,Enabled"\
  }:Register_enum.E_MBDET={\
    names="PRESENT,STANDALONE"\
  }:Register_enum.E_ON={\
    names="Off,On"\
  }:Register_enum.E_CASLAT={\
    names="resvd,resvd,2cyc,3cyc"\
  }:Register_enum.E_SDMEMSIZE={\
    names="16MB,32MB,64MB,128MB,256MB,resvd,resvd,resvd"\
  }:Register_enum.E_READY={\
    names="not avail.,ready"\
  }:Register_enum.E_SI_ID={\
    names="unknown,TI,TSMC,ST,resvd"\
  }:Register_enum.E_AUX_OD={\
    names="div0,div2,div8,div4,div5,div7,div9,div6"\
  }:Register_enum.E_VECTORS={\
    names="0x00000000,0xFFFF0000"\
  }:Register_enum.E_ID={\
    names="CM0,CM1,CM2,CM3"\
  }:Register_enum.E_DIMM={\
    names="...,...,...,...,...,...,...,...,16MB,32MB,64MB,128MB,256MB,...,...,..."\
  }:Register.G_CM_ID={\
    start=0x0000:length=4:base=M_CM_Regs:type=unsigned:read_only=False:\
        gui_name="ID":bit_fields.B_REV_A={\
      size=4:read_only=False:gui_name="REV"\
    }:bit_fields.B_BUILD_A={\
      position=4:size=8:gui_name="Build"\
    }:bit_fields.B_FPGA_A={\
      position=12:size=4:gui_name="FPGA"\
    }:bit_fields.B_ARCH_A={\
      position=16:size=8:gui_name="ARCH"\
    }:bit_fields.B_MAN_A={\
      position=24:size=8:gui_name="MAN"\
    }\
  }:Register.G_CM_PROC={\
    start=0x0004:length=4:base=M_CM_Regs:type=unsigned:read_only=True:\
        gui_name="Processor":bit_fields.default={}\
  }:Register.G_CM_OSC={\
    start=0x0008:length=4:base=M_CM_Regs:type=unsigned:gui_name="Core Oscillator":\
        bit_fields.B_PLL_VDW_A={\
      position=0:size=8:gui_name="PLL_VDW"\
    }:bit_fields.B_BMODE_A={\
      position=23:size=2:gui_name="BMODE"\
    }\
  }:Register.G_CM_CTRL={\
    start=0x000C:length=4:base=M_CM_Regs:gui_name="Control":bit_fields.B_LED_A={\
      position=0:size=1:enum=E_ON:read_only=False:gui_name="LED"\
    }:bit_fields.B_NMBDET_A={\
      position=1:enum=E_MBDET:read_only=True:gui_name="Motherboard"\
    }:bit_fields.B_REMAP_A={\
      position=2:enum=E_ENABLE:gui_name="Remap"\
    }:bit_fields.B_RESET_A={\
      position=3:size=1:read_only=False:gui_name="Reset"\
    }\
  }:Register.G_CM_STAT={\
    start=0x0010:length=4:base=M_CM_Regs:read_only=True:gui_name="Status":\
        bit_fields.B_ID_A={\
      size=8:signed=False:enum=E_ID:read_only=True:gui_name="Position"\
    }:bit_fields.B_SI_ID_A={\
      position=8:size=8:signed=False:enum=E_SI_ID:read_only=True:gui_name="Man.ID"\
    }:bit_fields.B_SSRAMSIZE_A={\
      position=16:size=8:read_only=True:gui_name="SSRAM"\
    }\
  }:Register.G_CM_LOCK={\
    start=0x0014:length=4:base=M_CM_Regs:gui_name="Lock":bit_fields.B_LOCKVAL_A={\
      size=16:read_only=False:gui_name="Lock Value"\
    }:bit_fields.B_LOCKED_A={\
      position=16:enum=E_ENABLE:read_only=True:gui_name="Locked"\
    }\
  }:Register.G_CM_LMBUSCNT={\
    start=0x0018:length=4:base=M_CM_Regs:read_only=True:\
        gui_name="Bus Cycle Counter":bit_fields.default={}\
  }:Register.G_CM_AUXOSC={\
    start=0x001C:length=4:base=M_CM_Regs:gui_name="Auxiliary Oscillator":\
        bit_fields.B_AUX_VDW_A={\
      size=9:gui_name="AUX_VDW"\
    }:bit_fields.B_AUX_RDW_A={\
      position=9:size=7:gui_name="AUX_RDW"\
    }:bit_fields.B_AUX_OD_A={\
      position=16:size=3:enum=E_AUX_OD:gui_name="AUX_OD"\
    }:bit_fields.B_PLLCTRL_A={\
      position=20:size=2:gui_name="PLL_CTRL"\
    }:bit_fields.B_PLLREFDIV_A={\
      position=24:size=4:gui_name="PLL_REF_DIV"\
    }:bit_fields.B_PLLOUTDIV_A={\
      position=2:size=4:gui_name="PLL_OUT_DIV"\
    }\
  }:Register.G_CM_SDRAM={\
    start=0x0020:length=4:base=M_CM_Regs:gui_name="SDRAM":bit_fields.B_CASLAT={\
      size=2:enum=E_CASLAT:gui_name="CAS Latency"\
    }:bit_fields.B_MEMSIZE={\
      position=2:size=3:enum=E_SDMEMSIZE:gui_name="MEMSIZE"\
    }:bit_fields.B_SPDOK={\
      position=5:gui_name="SPDOK"\
    }:bit_fields.B_NROWS={\
      position=8:size=4:gui_name="rows"\
    }:bit_fields.B_NCOLS={\
      position=12:size=4:gui_name="columns"\
    }:bit_fields.B_NBANKS={\
      position=16:size=4:gui_name="banks"\
    }\
  }:Register.G_CM_INIT={\
    start=0x0024:length=4:base=M_CM_Regs:gui_name="Initialization":\
        bit_fields.B_PLLBYPASS={\
      size=1:enum=E_ON:gui_name="PLL_BYPASS"\
    }:bit_fields.B_VINITHI={\
      position=2:enum=E_VECTORS:gui_name="Vector."\
    }:bit_fields.B_HCLKDIV={\
      position=4:size=3:gui_name="HCLK Divider"\
    }:bit_fields.B_PLLFBDIV={\
      position=8:size=8:gui_name="PLL_FB_DIV"\
    }:bit_fields.B_USERIN={\
      position=24:size=6:read_only=True:gui_name="User pins"\
    }:bit_fields.B_INITRAM={\
      position=16:gui_name="INITRAM"\
    }\
  }:Register.G_CM_REFCNT={\
    start=0x0028:length=4:base=M_CM_Regs:read_only=True:\
        gui_name="Reference Clock Cycle Counter":bit_fields.default={}\
  }:Register.G_CM_FLAGS={\
    start=0x0030:length=4:base=M_CM_Regs:read_only=True:gui_name="Flags":\
        bit_fields.default={}\
  }:Register.G_CM_FLAGSS={\
    start=0x0030:length=4:base=M_CM_Regs:write_only=True:gui_name="Set":\
        bit_fields.default={}\
  }:Register.G_CM_FLAGSC={\
    start=0x0034:length=4:base=M_CM_Regs:write_only=True:gui_name="Clear":\
        bit_fields.default={}\
  }:Register.G_CM_NVFLAGS={\
    start=0x0038:length=4:base=M_CM_Regs:read_only=True:\
        gui_name="Nonvolatile Flags":bit_fields.default={}\
  }:Register.G_CM_NVFLAGSS={\
    start=0x0038:length=4:base=M_CM_Regs:gui_name="nvSet":bit_fields.default={}\
  }:Register.G_CM_NVFLAGSC={\
    start=0x003C:length=4:base=M_CM_Regs:read_only=False:gui_name="nvClear":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_STAT={\
    start=0x0040:length=4:base=M_CM_Regs:read_only=True:gui_name="Status":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_RSTAT={\
    start=0x0044:length=4:base=M_CM_Regs:read_only=True:gui_name="Raw Status":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_ENSET={\
    start=0x0048:length=4:base=M_CM_Regs:read_only=False:gui_name="Enable Set":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_ENCLR={\
    start=0x004C:length=4:base=M_CM_Regs:gui_name="Enable Clear":\
        bit_fields.default={}\
  }:Register.G_CM_SOFT_INTSET={\
    start=0x0050:length=4:base=M_CM_Regs:gui_name="Interrupt Set":\
        bit_fields.default={}\
  }:Register.G_CM_SOFT_INTCLR={\
    start=0x0054:length=4:base=M_CM_Regs:gui_name="Interrupt Clear":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_STAT={\
    start=0x0060:length=4:base=M_CM_Regs:read_only=True:gui_name="Status":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_RSTAT={\
    start=0x0064:length=4:base=M_CM_Regs:read_only=True:gui_name="Raw Status":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_ENSET={\
    start=0x0068:length=4:base=M_CM_Regs:gui_name="Enable Set":bit_fields.default={}\
  }:Register.G_CM_FIQ_ENCLR={\
    start=0x006C:length=4:base=M_CM_Regs:gui_name="Enable Clear":\
        bit_fields.default={}\
  }:Register.G_CM_SPD={\
    start=0x0100:length=32:base=M_CM_Regs:read_only=True:\
        gui_name="SDRAM SPD Memory":bit_fields.default={}\
  }:Register.G_CM_VOLTAGE_CTL0={\
    start=0x0080:length=4:bit_fields.B_CORE_DAC_A={\
      size=8:gui_name="CORE_DAC"\
    }:bit_fields.B_VDDCORE={\
      position=8:size=12:read_only=True:gui_name="VDDCORE"\
    }:bit_fields.B_VDDCORE_DIFF1={\
      position=20:size=12:read_only=True:gui_name="VDDCORE_DIFF1"\
    }\
  }:Register.G_CM_VOLTAGE_CTL1={\
    start=0x0084:length=4:read_only=True:bit_fields.B_VDDIO={\
      position=8:size=12:read_only=True:gui_name="VDDIO"\
    }:bit_fields.B_VDDCORE_DIFF2={\
      position=20:size=12:read_only=True:gui_name="VDDCORE_DIFF2"\
    }\
  }:Register.G_CM_VOLTAGE_CTL2={\
    start=0x0088:length=4:read_only=True:bit_fields.B_VDDLEVEL={\
      position=8:size=12:read_only=True:gui_name="VDDLEVEL"\
    }:bit_fields.B_VDDCORE_DIFF3={\
      position=20:size=12:read_only=True:gui_name="VDDCORE_DIFF3"\
    }\
  }:Register.G_CM_VOLTAGE_CTL3={\
    start=0x008C:length=4:read_only=True:bit_fields.B_VDDPLL={\
      position=8:size=12:read_only=True:gui_name="VDDPLL"\
    }:bit_fields.B_VDDCORE_DIFF4={\
      position=20:size=12:read_only=True:gui_name="VDDCORE_DIFF4"\
    }\
  }:Concat_Register.default={}:Peripherals.default={\
    Register.default={\
      bit_fields.default={}\
    }\
  }:Register_Window.CM926EJ-S={\
    line="B_NMBDET_A,B_REMAP_A,B_LED_A":line="=B_ID_A,B_MEMSIZE":\
        line="G_CM_REFCNT":line="_":line="$+":line="_ID":\
        line="B_MAN_A,B_ARCH_A,B_FPGA_A,B_BUILD_A,B_REV_A":line="=G_CM_PROC":line="$+":\
        line="_Oscillator":line="B_BMODE_A,B_PLL_VDW_A":\
        line="B_PLLOUTDIV_A,B_PLLREFDIV_A,B_PLLCTRL_A,B_AUX_OD_A,B_AUX_RDW_A,B_AUX_VDW\
        _A":line="B_LOCKED_A,B_LOCKVAL_A":line="$+":line="_Control":\
        line="=B_RESET_A,B_REMAP_A,B_NMBDET_A,B_LED_A":line="$+":line="_Status":\
        line="B_SSRAMSIZE_A":line="B_SI_ID_A":line="$+":line="_SDRAM":\
        line="B_NBANKS,B_NCOLS,B_SPDOK,B_MEMSIZE,B_CASLAT":line="=B_NCOLS":\
        line="=B_NROWS":line="=B_SPDOK":line="=B_MEMSIZE":line="=B_CASLAT":line="$+":\
        line="_Initalization":line="B_PLLBYPASS,B_HCLKDIV,B_PLLFBDIV":line="B_USERIN":\
        line="=B_VINITHI,B_INITRAM":line="$+":line="_Flags":\
        line="G_CM_FLAGSS,G_CM_FLAGSC":line="G_CM_NVFLAGSS,G_CM_NVFLAGSC":line="$+":\
        line="_IRQ":line="=G_CM_IRQ_STAT":line="=G_CM_IRQ_RSTAT":\
        line="=G_CM_IRQ_ENSET":line="=G_CM_IRQ_ENCLR":line="$+":line="_Soft IRQ":\
        line="=G_CM_SOFT_INTSET":line="=G_CM_SOFT_INTCLR":line="$+":line="_FIQ":\
        line="=G_CM_FIQ_STAT":line="=G_CM_FIQ_RSTAT":line="=G_CM_FIQ_ENSET":\
        line="=G_CM_FIQ_ENCLR":line="$+":line="_VOLTAGE Control":\
        line="B_VDDCORE_DIFF1,B_VDDCORE,B_CORE_DAC_A":line="B_VDDCORE_DIFF2,B_VDDIO":\
        line="B_VDDCORE_DIFF3,B_VDDLEVEL":line="B_VDDCORE_DIFF4,B_VDDPLL"\
  }:ARM_config={\
    top_memory=0x40000\
  }\
}
description="ARM926EJ-S Core Module"