cm922texcal.bcd

realview22.rar

    start=0x0200:length=4:base=M_Stripe:gui_name="Timer 0 Control":\
        bit_fields.B_TIMER0_CR_MODE={\
      size=2:enum=E_TIMEMODE:gui_name="Mode"\
    }:bit_fields.B_TIMER0_CR_IE={\
      position=2:enum=E_ON:gui_name="Interrupt Enable"\
    }:bit_fields.B_TIMER0_CR_CI={\
      position=3:gui_name="Clear Interrupt"\
    }:bit_fields.B_TIMER0_CR_S={\
      position=4:enum=E_ON:gui_name="Running"\
    }\
  }:Register.G_SR_TIMER0_PRE={\
    start=0x0210:length=4:base=M_Stripe:gui_name="Timer 0 Pre-scaler ratio":\
        bit_fields.default={}\
  }:Register.G_SR_TIMER0_LIMIT={\
    start=0x0220:length=4:base=M_Stripe:gui_name="Timer 0 Limit":\
        bit_fields.default={}\
  }:Register.G_SR_TIMER0_READ={\
    start=0x0230:length=4:read_only=True:gui_name="Timer 0 Read":\
        bit_fields.default={}\
  }:Register.G_SR_TIMER1_CR={\
    start=0x0240:length=4:base=M_Stripe:gui_name="Timer 0 Control":\
        bit_fields.B_TIMER1_CR_MODE={\
      size=2:enum=E_TIMEMODE:gui_name="Mode"\
    }:bit_fields.B_TIMER1_CR_IE={\
      position=2:enum=E_ON:gui_name="Interrupt Enable"\
    }:bit_fields.B_TIMER1_CR_CI={\
      position=3:gui_name="Clear Interrupt"\
    }:bit_fields.B_TIMER1_CR_S={\
      position=4:enum=E_ON:gui_name="Running"\
    }\
  }:Register.G_SR_TIMER1_PRE={\
    start=0x0250:length=4:base=M_Stripe:gui_name="Timer 0 Pre-scaler ratio":\
        bit_fields.default={}\
  }:Register.G_SR_TIMER1_LIMIT={\
    start=0x0260:length=4:base=M_Stripe:gui_name="Timer 0 Limit":\
        bit_fields.default={}\
  }:Register.G_SR_TIMER1_READ={\
    start=0x0270:length=4:read_only=True:gui_name="Timer 0 Read":\
        bit_fields.default={}\
  }:Register.G_SR_UART_MC={\
    start=0x02A8:length=4:base=M_Stripe:gui_name="UART Mode Config":\
        bit_fields.B_UART_MC_CLS={\
      size=2:enum=E_CHARLNG:gui_name="Character Length"\
    }:bit_fields.B_UART_MC_ST={\
      position=2:enum=E_STOPBIT:gui_name="Stop Bit"\
    }:bit_fields.B_UART_MC_PE={\
      position=3:size=3:enum=E_PARITY:gui_name="Parity"\
    }\
  }:Register.G_SR_UART_DIVH={\
    start=0x02B8:length=4:base=M_Stripe:gui_name="UART Div Hi":\
        bit_fields.B_UART_DIVH={\
      size=8\
    }\
  }:Register.G_SR_UART_DIVL={\
    start=0x02B4:length=4:base=M_Stripe:gui_name="UART Div Lo":\
        bit_fields.B_UART_DIVL={\
      size=8\
    }\
  }:Register.G_SR_CLK_PLL1_NCNT={\
    start=0x0300:length=4:base=M_Stripe:gui_name="PLL1 N":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL1_MCNT={\
    start=0x0304:length=4:base=M_Stripe:gui_name="PLL1 M":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL1_KCNT={\
    start=0x0308:length=4:base=M_Stripe:gui_name="PLL1 K":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL1_CTRL={\
    start=0x030C:length=4:base=M_Stripe:gui_name="PLL1 CTRL":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL2_NCNT={\
    start=0x0310:length=4:base=M_Stripe:gui_name="PLL2 N":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL2_MCNT={\
    start=0x0314:length=4:base=M_Stripe:gui_name="PLL2 M":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL2_KCNT={\
    start=0x0318:length=4:base=M_Stripe:gui_name="PLL2 K":bit_fields.default={}\
  }:Register.G_SR_CLK_PLL2_CTRL={\
    start=0x031C:length=4:base=M_Stripe:gui_name="PLL2 CTRL":bit_fields.default={}\
  }:Register.G_SR_CLK_DERIVE={\
    start=0x0320:length=4:base=M_Stripe:gui_name="DERIVE":bit_fields.default={}\
  }:Register.G_SR_CLK_STATUS={\
    start=0x0324:length=4:base=M_Stripe:gui_name="STATUS":bit_fields.default={}\
  }:Register.G_SR_WDOG_CR={\
    start=0x0A00:length=4:base=M_Stripe:gui_name="Watchdog Control":\
        bit_fields.default={}\
  }:Register.G_SR_WDOG_COUNT={\
    start=0x0A04:length=4:base=M_Stripe:read_only=True:gui_name="Watchdog count":\
        bit_fields.default={}\
  }:Register.G_SR_WDOG_RELOAD={\
    start=0x0A08:length=4:base=M_Stripe:write_only=True:gui_name="Watchdog reload":\
        bit_fields.default={}\
  }:Register.G_SR_INT_MASKSET={\
    start=0x0C00:length=4:base=M_Stripe:gui_name="Interrupt Mask Set":\
        bit_fields.B_INT_MASKSET_PLD={\
      size=6:gui_name="PLD"\
    }:bit_fields.B_INT_MASKSET_EXT={\
      position=6:gui_name="EXT"\
    }:bit_fields.B_INT_MASKSET_UART={\
      position=7:gui_name="UART"\
    }:bit_fields.B_INT_MASKSET_TIMERS={\
      position=8:size=2:gui_name="TIMERS"\
    }:bit_fields.B_INT_MASKSET_PLL={\
      position=10:gui_name="PLL"\
    }:bit_fields.B_INT_MASKSET_EBI={\
      position=11:gui_name="EBI"\
    }:bit_fields.B_INT_MASKSET_BRIDGE={\
      position=12:size=2:gui_name="BRIDGES"\
    }:bit_fields.B_INT_MASKSET_DEBUG={\
      position=16:gui_name="FAST"\
    }:bit_fields.B_INT_MASKSET_FAST={\
      position=14:size=2:gui_name="COMM"\
    }\
  }:Register.G_SR_INT_MASKCLEAR={\
    start=0x0C04:length=4:base=M_Stripe:gui_name="Interrupt Mask Clear":\
        bit_fields.B_INT_MASKCLR_PLD={\
      size=6:gui_name="PLD"\
    }:bit_fields.B_INT_MASKCLR_EXT={\
      position=6:gui_name="EXT"\
    }:bit_fields.B_INT_MASKCLR_UART={\
      position=7:gui_name="UART"\
    }:bit_fields.B_INT_MASKCLR_PLL={\
      position=10:gui_name="PLL"\
    }:bit_fields.B_INT_MASKCLR_EBI={\
      position=11:gui_name="EBI"\
    }:bit_fields.B_INT_MASKCLR_BRIDGE={\
      position=12:size=2:gui_name="BRIDGES"\
    }:bit_fields.B_INT_MASKCLR_DEBUG={\
      position=16:gui_name="FAST"\
    }:bit_fields.B_INT_MASKCLR_FAST={\
      position=14:size=2:gui_name="COMM"\
    }:bit_fields.B_INT_MASKCLR_TIMERS={\
      position=8:size=2:gui_name="TIMERS"\
    }\
  }:Register.G_SR_INT_SRCSTAT={\
    start=0x0C08:length=4:base=M_Stripe:read_only=True:\
        gui_name="Interrupt Source Status":bit_fields.B_INT_SRCSTAT_PLD={\
      size=6:gui_name="PLD"\
    }:bit_fields.B_INT_SRCSTAT_EXT={\
      position=6:gui_name="EXT"\
    }:bit_fields.B_INT_SRCSTAT_UART={\
      position=7:gui_name="UART"\
    }:bit_fields.B_INT_SRCSTAT_PLL={\
      position=10:gui_name="PLL"\
    }:bit_fields.B_INT_SRCSTAT_EBI={\
      position=11:gui_name="EBI"\
    }:bit_fields.B_INT_SRCSTAT_BRIDGE={\
      position=12:size=2:gui_name="BRIDGES"\
    }:bit_fields.B_INT_SRCSTAT_DEBUG={\
      position=16:gui_name="FAST"\
    }:bit_fields.B_INT_SRCSTAT_FAST={\
      position=14:size=2:gui_name="COMM"\
    }:bit_fields.B_INT_SRCSTAT_TIMERS={\
      position=8:size=2:gui_name="TIMERS"\
    }\
  }:Register.G_SR_INT_REQSTAT={\
    start=0x0C08:length=4:base=M_Stripe:read_only=True:\
        gui_name="Interrupt Source Status":bit_fields.B_INT_REQSTAT_PLD={\
      size=6:gui_name="PLD"\
    }:bit_fields.B_INT_REQSTAT_EXT={\
      position=6:gui_name="EXT"\
    }:bit_fields.B_INT_REQSTAT_UART={\
      position=7:gui_name="UART"\
    }:bit_fields.B_INT_REQSTAT_PLL={\
      position=10:gui_name="PLL"\
    }:bit_fields.B_INT_REQSTAT_EBI={\
      position=11:gui_name="EBI"\
    }:bit_fields.B_INT_REQSTAT_BRIDGE={\
      position=12:size=2:gui_name="BRIDGES"\
    }:bit_fields.B_INT_REQSTAT_DEBUG={\
      position=16:gui_name="FAST"\
    }:bit_fields.B_INT_REQSTAT_FAST={\
      position=14:size=2:gui_name="COMM"\
    }:bit_fields.B_INT_REQSTAT_TIMERS={\
      position=8:size=2:gui_name="TIMERS"\
    }\
  }:Register.G_SR_INT_ID={\
    start=0x0C10:length=4:base=M_Stripe:read_only=True:gui_name="Interrupt ID":\
        bit_fields.B_INT_ID_ID={\
      size=6:gui_name="Active Priority"\
    }\
  }:Register.G_SR_INT_PLDPRI={\
    start=0x0C14:length=4:read_only=True:bit_fields.B_INT_PLDPRI_PRI={\
      size=6:gui_name="PLD PRIORITY"\
    }\
  }:Register.G_SR_INT_MODE={\
    bit_fields.B_INT_MODE_MODE={\
      size=2:enum=E_INTMODE:gui_name="MODE"\
    }\
  }:Concat_Register.G_SR_UART_DIV={\
    low_name="B_UART_DIVL":low_mask=0x00FF:high_shift=0xFFFFFFE8:high_mask=0xFF00:\
        length=2:gui_name="UART Div"\
  }:Peripherals.default={\
    Register.default={\
      bit_fields.default={}\
    }\
  }:Register_Window.CM922T-ETM={\
    line="B_NMBDET_A,B_REMAP_A,B_MISCLED_A":line="=B_ID_A,B_DIMM":\
        line="G_CM_REFCNT":line="_":line="$+":line="_ID":\
        line="B_MAN_A,B_ARCH_A,B_FPGA_A,B_BUILD_A,B_REV_A":line="=G_CM_PROC":line="$+":\
        line="_Oscillator":line="B_OSCAVDW,B_OSCAOD":line="B_OSCBVDW,B_OSCBOD":\
        line="B_OSCBUSM":line="B_LOCKED_A,B_LOCKVAL_A":line="$+":line="_Control":\
        line="=B_RESET_A":\
        line="B_USRLED0_A,B_USRLED1_A,B_USRLED2_A,B_USRLED3_A,B_USRLED4_A,B_USRLED5_A,\
        B_USRLED6_A,B_USRLED7_A":line="$+":line="_Status":line="B_SSRAMSIZE_A":\
        line="B_SI_ID_A":\
        line="B_USRSW0_A,B_USRSW1_A,B_USRSW2_A,B_USRSW3_A,B_USRSW4_A,B_USRSW5_A,B_USRS\
        W6_A,B_USRSW7_A":line="$+":line="_SDRAM":line="=B_NBANKS":line="=B_NCOLS":\
        line="=B_NROWS":line="=B_SPDOK":line="=B_MEMSIZE":line="=B_CASLAT":line="$+":\
        line="_Flags":line="G_CM_FLAGSS,G_CM_FLAGSC":\
        line="G_CM_NVFLAGSS,G_CM_NVFLAGSC":line="$+":line="_IRQ":line="=G_CM_IRQ_STAT":\
        line="=G_CM_IRQ_RSTAT":line="=G_CM_IRQ_ENSET":line="=G_CM_IRQ_ENCLR":line="$+":\
        line="_Soft IRQ":line="=G_CM_SOFT_INTSET":line="=G_CM_SOFT_INTCLR":line="$+":\
        line="_FIQ":line="=G_CM_FIQ_STAT":line="=G_CM_FIQ_RSTAT":\
        line="=G_CM_FIQ_ENSET":line="=G_CM_FIQ_ENCLR"\
  }:Register_Window.Stripe={\
    line="$+":line="_Reset & Mode Control":\
        line="B_BOOTCR_RE,B_BOOTCR_HM,B_BOOTCR_BM":\
        line="B_RESETSR_ER,B_RESETSR_JT,B_RESETSR_CR,B_RESETSR_WR":line="G_SR_IDCODE":\
        line="G_SR_SRAM0_SR":line="G_SR_SRAM1_SR":\
        line="B_DPSRAM0_SIZE,B_DPSRAM0_GLBL,B_DPSRAM0_MODE":line="B_DPSRAM0_LCKADDR":\
        line="B_DPSRAM1_SIZE,B_DPSRAM1_GLBL,B_DPSRAM1_MODE":line="B_DPSRAM1_LCKADDR":\
        line="$+":line="_I/O Control":line="_SDRAM":\
        line="B_IOCRSDRAM_LK,B_IOCRSDRAM_IO,B_IOCRSDRAM_OC,B_IOCRSDRAM_IC":line="_EBI":\
        line="B_IOCREBI_LK,B_IOCREBI_IO,B_IOCREBI_OC,B_IOCREBI_IC":line="_UART":\
        line="B_IOCRUART_LK,B_IOCRUART_IO,B_IOCRUART_OC,B_IOCRUART_IC":line="_TRACE":\
        line="B_IOCRTRACE_LK,B_IOCRTRACE_IO,B_IOCRTRACE_OC,B_IOCRTRACE_IC":line="$+":\
        line="_Memory Map":line="_Stripe Registers":\
        line="B_MMAP_REGS_BASE,B_MMAP_REGS_SIZE,B_MMAP_REGS_NP,B_MMAP_REGS_EN":\
        line="_SRAM0":\
        line="B_MMAP_SRAM0_BASE,B_MMAP_SRAM0_SIZE,B_MMAP_SRAM0_NP,B_MMAP_SRAM0_EN":\
        line="_SRAM1":\
        line="B_MMAP_SRAM1_BASE,B_MMAP_SRAM1_SIZE,B_MMAP_SRAM1_NP,B_MMAP_SRAM1_EN":\
        line="_DPSRAM0":\
        line="B_MMAP_DPSR0_BASE,B_MMAP_DPSR0_SIZE,B_MMAP_DPSR0_NP,B_MMAP_DPSR0_EN":\
        line="_DPSRAM1":\
        line="B_MMAP_DPSR1_BASE,B_MMAP_DPSR1_SIZE,B_MMAP_DPSR1_NP,B_MMAP_DPSR1_EN":\
        line="_SDRAM0":\
        line="B_MMAP_SDRAM0_BASE,B_MMAP_SDRAM0_SIZE,B_MMAP_SDRAM0_NP,B_MMAP_SDRAM0_EN":\
        line="_SDRAM1":\
        line="B_MMAP_SDRAM1_BASE,B_MMAP_SDRAM1_SIZE,B_MMAP_SDRAM1_NP,B_MMAP_SDRAM1_EN":\
        line="_EBI0":\
        line="B_MMAP_EBI0_BASE,B_MMAP_EBI0_SIZE,B_MMAP_EBI0_NP,B_MMAP_EBI0_EN":\
        line="_EBI1":\
        line="B_MMAP_EBI1_BASE,B_MMAP_EBI1_SIZE,B_MMAP_EBI1_NP,B_MMAP_EBI1_EN":\
        line="_EBI2":\
        line="B_MMAP_EBI2_BASE,B_MMAP_EBI2_SIZE,B_MMAP_EBI2_NP,B_MMAP_EBI2_EN":\
        line="_EBI3":\
        line="B_MMAP_EBI3_BASE,B_MMAP_EBI3_SIZE,B_MMAP_EBI3_NP,B_MMAP_EBI3_EN":\
        line="_PLD0":\
        line="B_MMAP_PLD0_BASE,B_MMAP_PLD0_SIZE,B_MMAP_PLD0_NP,B_MMAP_PLD0_EN":\
        line="_PLD1":\
        line="B_MMAP_PLD1_BASE,B_MMAP_PLD1_SIZE,B_MMAP_PLD1_NP,B_MMAP_PLD1_EN":\
        line="_PLD2":\
        line="B_MMAP_PLD2_BASE,B_MMAP_PLD2_SIZE,B_MMAP_PLD2_NP,B_MMAP_PLD2_EN":\
        line="_PLD3":\
        line="B_MMAP_PLD3_BASE,B_MMAP_PLD3_SIZE,B_MMAP_PLD3_NP,B_MMAP_PLD3_EN":\
        line="$+":line="_Bridges":line="_Stripe-PLD":\
        line="=B_PLDSB_CR_NW,B_PLDSB_CR_NP":\
        line="=B_PLDSB_SR_HBST,B_PLDSB_SR_HSZE,B_PLDSB_SR_HTRN,B_PLDSB_SR_WF":\
        line="=G_SR_PLDSB_ADDRSR":line="_PLD-Stripe":\
        line="=B_PLDMB_CR_NW,B_PLDMB_CR_NP":line="_AHB1-2":\
        line="=B_AHB12B_CR_NW,B_AHB12B_CR_NP":\
        line="=B_AHB12B_SR_HBST,B_AHB12B_SR_HSZE,B_AHB12B_SR_HTRN,B_AHB12B_SR_WF":\
        line="=G_SR_AHB12B_ADDRSR":line="$+":line="_Timers":\
        line="=B_TIMER0_CR_S,B_TIMER0_CR_CI,B_TIMER0_CR_IE,B_TIMER0_CR_MODE":\
        line="=G_SR_TIMER0_PRE":line="=G_SR_TIMER0_LIMIT":line="=G_SR_TIMER0_READ":\
        line="=G_SR_TIMER0_CR":\
        line="=B_TIMER1_CR_S,B_TIMER1_CR_CI,B_TIMER1_CR_IE,B_TIMER1_CR_MODE":\
        line="=G_SR_TIMER1_PRE":line="=G_SR_TIMER1_LIMIT":line="=G_SR_TIMER1_READ":\
        line="=G_SR_TIMER1_CR":line="$+":line="_UART":\
        line="=B_UART_MC_PE,B_UART_MC_ST,B_UART_MC_CLS":\
        line="=G_SR_UART_DIVH,G_SR_UART_DIVL":line="$+":line="_CLOCKS":\
        line="=G_SR_CLK_PLL1_NCNT":line="=G_SR_CLK_PLL1_MCNT":\
        line="=G_SR_CLK_PLL1_KCNT":line="=G_SR_CLK_PLL1_CTRL":\
        line="=G_SR_CLK_PLL2_NCNT":line="=G_SR_CLK_PLL2_MCNT":\
        line="=G_SR_CLK_PLL2_KCNT":line="=G_SR_CLK_PLL2_CTRL":line="=G_SR_CLK_DERIVE":\
        line="=G_SR_CLK_STATUS":line="$+":line="_Watchdog":line="=G_SR_WDOG_CR":\
        line="=G_SR_WDOG_COUNT":line="=G_SR_WDOG_RELOAD":line="$+":line="_Interrupts":\
        line="_Mask Set":\
        line="B_INT_MASKSET_FAST,B_INT_MASKSET_DEBUG,B_INT_MASKSET_BRIDGE,B_INT_MASKSE\
        T_EBI,B_INT_MASKSET_PLL,B_INT_MASKSET_TIMERS,B_INT_MASKSET_UART,B_INT_MASKSET_\
        EXT,B_INT_MASKSET_PLD":line="_Mask Clear":\
        line="B_INT_MASKCLR_FAST,B_INT_MASKCLR_DEBUG,B_INT_MASKCLR_BRIDGE,B_INT_MASKCL\
        R_EBI,B_INT_MASKCLR_PLL,B_INT_MASKCLR_TIMERS,B_INT_MASKCLR_UART,B_INT_MASKCLR_\
        EXT,B_INT_MASKCLR_PLD":line="_Source Status":\
        line="B_INT_SRCSTAT_FAST,B_INT_SRCSTAT_DEBUG,B_INT_SRCSTAT_BRIDGE,B_INT_SRCSTA\
        T_EBI,B_INT_SRCSTAT_PLL,B_INT_SRCSTAT_TIMERS,B_INT_SRCSTAT_UART,B_INT_SRCSTAT_\
        EXT,B_INT_SRCSTAT_PLD":line="_Request Status":\
        line="B_INT_REQSTAT_FAST,B_INT_REQSTAT_DEBUG,B_INT_REQSTAT_BRIDGE,B_INT_REQSTA\
        T_EBI,B_INT_REQSTAT_PLL,B_INT_REQSTAT_TIMERS,B_INT_REQSTAT_UART,B_INT_REQSTAT_\
        EXT,B_INT_REQSTAT_PLD":line="=B_INT_ID_ID":line="=B_INT_PLDPRI_PRI":\
        line="=B_INT_MODE_MODE"\
  }:ARM_config={\
    top_memory=0x8000000\
  }\
}