cm922texcal.bcd

realview22.rar

  }:Register.G_SR_RESET_SR={\
    start=0x0004:length=4:base=M_Stripe:gui_name="Reset Status":\
        bit_fields.B_RESETSR_WR={\
      gui_name="Watchdog"\
    }:bit_fields.B_RESETSR_CR={\
      position=1:gui_name="Config"\
    }:bit_fields.B_RESETSR_JT={\
      position=2:gui_name="JTAG"\
    }:bit_fields.B_RESETSR_ER={\
      position=3:gui_name="External"\
    }\
  }:Register.G_SR_IDCODE={\
    start=0x0008:length=4:base=M_Stripe:read_only=True:gui_name="ID Code":\
        bit_fields.default={}\
  }:Register.G_SR_SRAM0_SR={\
    start=0x0020:length=4:base=M_Stripe:read_only=True:gui_name="SRAM0 Size":\
        bit_fields.default={}\
  }:Register.G_SR_SRAM1_SR={\
    start=0x0024:length=4:base=M_Stripe:read_only=True:gui_name="SRAM1 Size":\
        bit_fields.default={}\
  }:Register.G_SR_DPSRAM0_SR={\
    start=0x0030:length=4:base=M_Stripe:read_only=True:gui_name="DPSRAM0 Status":\
        bit_fields.B_DPSRAM0_MODE={\
      size=4:gui_name="DPSRAM0 Mode"\
    }:bit_fields.B_DPSRAM0_GLBL={\
      position=4:size=2:enum=E_DPSRAM_MODE:gui_name="Global DP mode"\
    }:bit_fields.B_DPSRAM0_SIZE={\
      position=12:size=20:gui_name="DPSRAM0 Size"\
    }\
  }:Register.G_SR_DPSRAM0_LCR={\
    start=0x0034:length=4:base=M_Stripe:gui_name="DPSRAM0 LCK":\
        bit_fields.B_DPSRAM0_LCKADDR={\
      position=5:size=12:gui_name="DPSRAM0 LCKADDR"\
    }\
  }:Register.G_SR_DPSRAM1_SR={\
    start=0x0038:length=4:base=M_Stripe:read_only=True:gui_name="DPSRAM1 Status":\
        bit_fields.B_DPSRAM1_MODE={\
      size=4:gui_name="DPSRAM0 Mode"\
    }:bit_fields.B_DPSRAM1_GLBL={\
      position=4:size=2:enum=E_DPSRAM_MODE:gui_name="Global DP mode"\
    }:bit_fields.B_DPSRAM1_SIZE={\
      position=12:size=20:gui_name="DPSRAM0 Size"\
    }\
  }:Register.G_SR_DPSRAM1_LCR={\
    start=0x003C:length=4:base=M_Stripe:gui_name="DPSRAM1 LCK":\
        bit_fields.B_DPSRAM1_LCKADDR={\
      position=5:size=12:gui_name="DPSRAM1 LCKADDR"\
    }\
  }:Register.G_SR_IOCR_SDRAM={\
    start=0x0040:length=4:base=M_Stripe:gui_name="SDRAM":bit_fields.B_IOCRSDRAM_LK={\
      gui_name="Lock"\
    }:bit_fields.B_IOCRSDRAM_IO={\
      position=1:enum=E_IOCR_IO:gui_name="Bank"\
    }:bit_fields.B_IOCRSDRAM_OC={\
      position=2:size=3:enum=E_IOCR_OC:gui_name="Output"\
    }:bit_fields.B_IOCRSDRAM_IC={\
      position=5:size=2:enum=E_IOCR_IC:gui_name="Input"\
    }\
  }:Register.G_SR_IOCR_EBI={\
    start=0x0044:length=4:base=M_Stripe:gui_name="EBI":bit_fields.B_IOCREBI_LK={\
      gui_name="Lock"\
    }:bit_fields.B_IOCREBI_IO={\
      position=1:enum=E_IOCR_IO:gui_name="Bank"\
    }:bit_fields.B_IOCREBI_OC={\
      position=2:size=3:enum=E_IOCR_OC:gui_name="Output"\
    }:bit_fields.B_IOCREBI_IC={\
      position=5:size=2:enum=E_IOCR_IC:gui_name="Input"\
    }\
  }:Register.G_SR_IOCR_UART={\
    start=0x0048:length=4:base=M_Stripe:gui_name="UART":bit_fields.B_IOCRUART_LK={\
      gui_name="Lock"\
    }:bit_fields.B_IOCRUART_IO={\
      position=1:enum=E_IOCR_IO:gui_name="Bank"\
    }:bit_fields.B_IOCRUART_OC={\
      position=2:size=3:enum=E_IOCR_OC:gui_name="Output"\
    }:bit_fields.B_IOCRUART_IC={\
      position=5:size=2:enum=E_IOCR_IC:gui_name="Input"\
    }\
  }:Register.G_SR_IOCR_TRACE={\
    start=0x004C:length=4:base=M_Stripe:gui_name="TRACE":bit_fields.B_IOCRTRACE_LK={\
      gui_name="Lock"\
    }:bit_fields.B_IOCRTRACE_IO={\
      position=1:enum=E_IOCR_IO:gui_name="Bank"\
    }:bit_fields.B_IOCRTRACE_OC={\
      position=2:size=3:enum=E_IOCR_OC:gui_name="Output"\
    }:bit_fields.B_IOCRTRACE_IC={\
      position=5:size=2:enum=E_IOCR_IC:gui_name="Input"\
    }\
  }:Register.G_SR_MMAP_REGISTERS={\
    start=0x0080:length=4:base=M_Stripe:gui_name="Registers":\
        bit_fields.B_MMAP_REGS_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_REGS_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_REGS_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_REGS_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_SRAM0={\
    start=0x0090:length=4:base=M_Stripe:gui_name="SRAM0":bit_fields.B_MMAP_SRAM0_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_SRAM0_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_SRAM0_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_SRAM0_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_SRAM1={\
    start=0x0094:length=4:base=M_Stripe:gui_name="SRAM1":bit_fields.B_MMAP_SRAM1_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_SRAM1_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_SRAM1_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_SRAM1_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_DPSRAM0={\
    start=0x00A0:length=4:base=M_Stripe:gui_name="DPSRAM0":\
        bit_fields.B_MMAP_DPSR0_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_DPSR0_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_DPSR0_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_DPSR0_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_DPSRAM1={\
    start=0x00A4:length=4:base=M_Stripe:gui_name="DPSRAM1":\
        bit_fields.B_MMAP_DPSR1_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_DPSR1_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_DPSR1_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_DPSR1_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_SDRAM0={\
    start=0x00B0:length=4:base=M_Stripe:gui_name="SDRAM0":\
        bit_fields.B_MMAP_SDRAM0_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_SDRAM0_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_SDRAM0_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_SDRAM0_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_SDRAM1={\
    start=0x00B4:length=4:base=M_Stripe:gui_name="SDRAM1":\
        bit_fields.B_MMAP_SDRAM1_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_SDRAM1_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_SDRAM1_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_SDRAM1_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_EBI0={\
    start=0x00C0:length=4:base=M_Stripe:gui_name="EBI0":bit_fields.B_MMAP_EBI0_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_EBI0_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_EBI0_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_EBI0_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_EBI1={\
    start=0x00C4:length=4:base=M_Stripe:gui_name="EBI1":bit_fields.B_MMAP_EBI1_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_EBI1_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_EBI1_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_EBI1_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_EBI2={\
    start=0x00C8:length=4:base=M_Stripe:gui_name="EBI2":bit_fields.B_MMAP_EBI2_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_EBI2_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_EBI2_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_EBI2_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_EBI3={\
    start=0x00CC:length=4:base=M_Stripe:gui_name="EBI3":bit_fields.B_MMAP_EBI3_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_EBI3_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_EBI3_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_EBI3_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_PLD0={\
    start=0x00D0:length=4:base=M_Stripe:gui_name="PLD0":bit_fields.B_MMAP_PLD0_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_PLD0_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_PLD0_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_PLD0_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_PLD1={\
    start=0x00D4:length=4:base=M_Stripe:gui_name="PLD1":bit_fields.B_MMAP_PLD1_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_PLD1_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_PLD1_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_PLD1_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_PLD2={\
    start=0x00D8:length=4:base=M_Stripe:gui_name="PLD2":bit_fields.B_MMAP_PLD2_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_PLD2_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_PLD2_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_PLD2_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_MMAP_PLD3={\
    start=0x00DC:length=4:base=M_Stripe:gui_name="PLD3":bit_fields.B_MMAP_PLD3_EN={\
      enum=E_ON:gui_name="Enabled"\
    }:bit_fields.B_MMAP_PLD3_NP={\
      position=1:gui_name="No Prefetch"\
    }:bit_fields.B_MMAP_PLD3_SIZE={\
      position=7:size=5:gui_name="Size"\
    }:bit_fields.B_MMAP_PLD3_BASE={\
      position=14:size=18:gui_name="Base"\
    }\
  }:Register.G_SR_AHB12B_CR={\
    start=0x0100:length=4:base=M_Stripe:gui_name="AHB1-2 control":\
        bit_fields.B_AHB12B_CR_NP={\
      enum=E_ON:gui_name="No Prefetch"\
    }:bit_fields.B_AHB12B_CR_NW={\
      position=1:enum=E_ON:gui_name="No Posting"\
    }\
  }:Register.G_SR_PLDSB_CR={\
    start=0x0110:length=4:base=M_Stripe:gui_name="Stripe to PLD control":\
        bit_fields.B_PLDSB_CR_NP={\
      enum=E_ON:gui_name="No Prefetch"\
    }:bit_fields.B_PLDSB_CR_NW={\
      position=1:enum=E_ON:gui_name="No Posting"\
    }\
  }:Register.G_SR_PLDSB_SR={\
    start=0x0118:length=4:base=M_Stripe:gui_name="Stripe-PLD bridge status":\
        bit_fields.B_PLDSB_SR_WF={\
      gui_name="Bus Error"\
    }:bit_fields.B_PLDSB_SR_HTRN={\
      position=1:size=2:enum=E_HTRANS:gui_name="HTRANS"\
    }:bit_fields.B_PLDSB_SR_HSZE={\
      position=3:size=3:enum=E_HSIZE:gui_name="HSIZE"\
    }:bit_fields.B_PLDSB_SR_HBST={\
      position=6:size=3:enum=E_HBURST:gui_name="HBURST"\
    }\
  }:Register.G_SR_PLDSB_ADDRSR={\
    start=0x0114:length=4:base=M_Stripe:read_only=True:\
        gui_name="Stripe-PLD bridge address status":bit_fields.default={}\
  }:Register.G_SR_PLDMB_CR={\
    start=0x0120:length=4:base=M_Stripe:gui_name="PLD-Stripe bridge control":\
        bit_fields.B_PLDMB_CR_NP={\
      enum=E_ON:gui_name="No Prefetch"\
    }:bit_fields.B_PLDMB_CR_NW={\
      position=1:enum=E_ON:gui_name="No Posting"\
    }\
  }:Register.G_SR_AHB12B_SR={\
    start=0x0800:length=4:base=M_Stripe:gui_name="AHB1-2 bridge status":\
        bit_fields.B_AHB12B_SR_WF={\
      gui_name="Bus Error"\
    }:bit_fields.B_AHB12B_SR_HTRN={\
      position=1:size=2:enum=E_HTRANS:gui_name="HTRANS"\
    }:bit_fields.B_AHB12B_SR_HSZE={\
      position=3:size=3:enum=E_HSIZE:gui_name="HSIZE"\
    }:bit_fields.B_AHB12B_SR_HBST={\
      position=6:size=3:enum=E_HBURST:gui_name="HBURST"\
    }\
  }:Register.G_SR_AHB12B_ADDRSR={\
    start=0x0804:length=4:base=M_Stripe:gui_name="AHB1-2 bridge address status":\
        bit_fields.default={}\
  }:Register.G_SR_TIMER0_CR={\