irlength.arm

multi-ice2.26.rar

; ARM TAP controller IR register lengths file
; Copyright (C) 2001-2004 ARM Limited. All rights reserved.
;
; RCS $Revision: 1.39.2.3.4.5 $
; Checkin $Date: 2004/03/02 08:51:19 $
; Revising $Author: sellis $
;
; This file contains a definition of the number of bits in the TAP controller's
; IR register for each core driver when used with the supplied TAP controller 
; from ARM. The IR register is accessed serially through the TDI and TDO pins so
; the register width i.e. number of bits is described as the register length by
; convention.
;
; This information is used to calculate the total number of bits that must be 
; shifted through TDI->TDO for multi-processor ASICs which have the TAP 
; controllers serially chained e.g. if three ARM7TDMI cores (each with their own
; TAP controllers) are fabricated onto a single ASIC, the TAP controllers will
; have their TDI->TDO pins serially chained. The 4 bits of IR register will
; appear in series giving a total chain length of 12 bits.
;
; A value of 0 indicates that the IR is shared with another processor i.e. 2 or
; more devices share a TAP controller. e.g. A Piccolo can only be used in
; conjunction with a host processor. It shares the host's TAP controller so the
; number of bits that must be scanned through the TAP when the IR is selected is
; no more than if it were not there. Furthermore, the IR length is determined by
; the host processor entry in this file so any IR length for a Piccolo has no 
; meaning. Any drivers that are referenced in the config file are expected to be
; present in this file so an entry must exist in order to use the driver name.
;
; User defined devices can be bypassed to get to the ARM cores if an entry is 
; made below and the driver is referenced in the config file e.g. if a user
; wants to place a DSP (with its own TAP controller) in the scan path i.e.
; serially chained TAP controllers, then an entry must be added below to define
; the IR length for the DSP e.g 'DSP=5' means the driver called DSP requires 5
; extra bits to be slotted into the scan chain to bypass the DSP's TAP
; controller when the debugger wants to access the ARM devices. The driver name
; 'DSP' can then be used in the config file without error.
;
;-------------------------------------------------------------------------------

; ARM7 series cores

ARM70DI=4
ARM7DMI=4
ARM7TDMI=4
ARM7TDMI-S=4
ARM7TDI-S=4
ARM710T=4
ARM720T=4
ARM740T=4
ARM7EJ-S=4
KS32C50100=4
S3C4510B=4

; ARM9 series cores

ARM9TDMI=4
ARM920T=4
ARM922T=4
ARM925T=4
ARM926EJ-S=4
ARM940T=4
ARM9E-S=4
ARM9EJ-S=4
ARM946E-S=4
ARM966E-S=4
ARM968E-S=4


; ARM946 devices in config mode

ARM946E-S_BS2=2
ARM946E-S_BS3=3
ARM946E-S_BS6=6

; ARM966 devices in config mode

ARM966_BS2=2
ARM966_BS3=3
ARM966_BS6=6
ARM966E-S_BS2=2
ARM966E-S_BS3=3
ARM966E-S_BS6=6

; ARM720Tr3 devices in config mode

ARM720Tr3_BS2=2
ARM720Tr3_BS3=3
ARM720Tr3_BS6=6

; ARM922Tr1 devices in config mode

ARM922Tr1_BS2=2
ARM922Tr1_BS3=3
ARM922Tr1_BS6=6

; ARM7TDMIr4 devices in config mode

ARM7TDMIr4_BS2=2
ARM7TDMIr4_BS3=3
ARM7TDMIr4_BS6=6

; ARM926EJ-Sr0 devices in config mode

ARM926EJ-S_BS2=2
ARM926EJ-S_BS3=3
ARM926EJ-S_BS6=6

; ARM926EJ-S PrimeXSys Platform DevChip in config mode

ARM926PXPdev_BS2=2

; ARM10 series cores

ARM1020T=4  ;ARM10 rev.0 core
ARM10200=4  ;ARM10 rev.0 with VFP
ARM1020E=4  ;ARM10 rev.1+ core
ARM10200E=4 ;ARM10 rev.1+ with VFP
ARM1022E=4  ;ARM10 rev.1+ core
ARM10220E=4 ;ARM10 rev.1+ with VFP
ARM1026EJ-S=4 ;ARM10EJ-S rev 0

; ARM10 devices in config mode
ARM1026EJr0_BS2=2
ARM1026EJ-Sr0_BS2=2

; ARM11 devices in config mode
ARM1136J-Sr0_BS2=2

; StrongARM and XScale devices

SA-1100=5
SA-1110=5
XScale=5
XScale-PXA250=5
XScale-PXA210=5
XScale-80200=5
XScale-80321=5
XScale-IXP425=7
XScale-IXP2400=7
XScale-IXP2800=7
XScale-IR7=7
GC80312=4   ;Intel support chip


; ARM core extensions

Piccolo=0   ;Shares its TAP controller with the host processor
IEU=0       ;Shares its TAP controller with the host processor
ETM=0       ;Shares its TAP controller with the host processor
ARMFLASH=5  ;Special name for ARM designed flash programmer TAP
ETMBUF=4    ;On Chip Trace buffer TAP controller


; Known DSPs and other 3rd party devices

LEAD3=38
S-GOLDlite_TCU=8


; PLDs and FPGAs used on ARM Boards

XC18V01=8
XC18V02=8
XC18V04=8
XC18V256=8
XC18V512=8
XC9536=8
XC9572=8
XC9536XL=8
XC9572XL=8
XC4036XL=3
XC4062XL=3
XC4036XLA=3
XC4062XLA=3
XC4085XLA=3
XC95288XV=8
XC95144XL=8
XCV300=5
XCV400=5
XCV600=5
XCV800=5
XCV1000=5
XCV600E=5
XCV1000E=5
XCV1600E=5
XCV2000E=5
XCV2600E=5
XCV3200E=5
XCR3128=4
XC2V2000=6
XC2V4000=6
XC2V6000=6
XC2V8000=6
XC2V10000=6
; Typo for XC2S200E
XCS200E=5
XC2S200E=5
XC2S300E=5
XC2S400E=5
PZ3128=4
EP20K400E=10
EP20K600E=10
EP20K1000E=10
EP2A40=10
EP2A70=10
EPF10K200E=10
EPM3032A=10
EPM7064AE=10
EPM7256AE=10
EPM7512AE=10
EPXA10=10 

; end of file irlength.arm