📄 vdk-bf537.ldf
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/*
** Default LDF for a VDK project on the ADSP-BF537.
**
** There are configuration options that can be specified either by compiler
** flags, or by linker flags directly. These options are:
**
** __WORKAROUNDS_ENABLED
** Defined by compiler when -workaround is used to direct LDF to
** link with libraries that have been built with work-arounds enabled.
** USE_CACHE
** Makes use of some L1 memory as cache. Implies the presence of at
** least some external memory.
** USE_SDRAM
** Makes SDRAM available as standard program/data memory, with no
** cache configuration of L1. Heap space is moved into SDRAM.
** USER_CRT
** Specifies a custom or System Builder generated CRT object to use.
** _ADI_LIBIO
** Use the ADI io library (default and fast)
** _DINKUM_IO
** Use dinkum io library (slower but more compatible). Enabled
** by the flag -cstd-io
*/
// Setup the architecture
ARCHITECTURE(ADSP-BF537)
// Setup the search directories
SEARCH_DIR( $ADI_DSP/BLACKFIN/lib )
// Include the VDK preprocessor macros
#define VDK_LDF_
#include "VDK.h"
// Setup the VDK library preprocessor macros
#if VDK_INSTRUMENTATION_LEVEL_==2
#define VDK_IFLAG_ i
#elif VDK_INSTRUMENTATION_LEVEL_==1
#define VDK_IFLAG_ e
#else
#define VDK_IFLAG_ n
#endif
#define VDK_LIB_NAME_MACRO_(x) vdk- ## x ## -BF532.dlb
#ifdef __WORKAROUNDS_ENABLED
#ifdef __ADI_LIBEH__
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## yx.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#else /* __ADI_LIBEH__ */
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#endif
#else /* __WORKAROUNDS_ENABLED */
#ifdef __ADI_LIBEH__
#define RT_LIB_NAME(x) lib ## x ## .dlb
#define RT_LIB_NAME_EH(x) lib ## x ## x.dlb
#define RT_OBJ_NAME(x) x ## .doj
#else /* __ADI_LIBEH__ */
#define RT_LIB_NAME(x) lib ## x ## .dlb
#define RT_LIB_NAME_EH(x) lib ## x ## .dlb
#define RT_OBJ_NAME(x) x ## .doj
#endif
#endif /* __WORKAROUNDS_ENABLED */
#ifdef USER_CRT
#define CRT USER_CRT
#else
#define CRT RT_OBJ_NAME(crtsfc532)
#endif
#define OMEGA RT_OBJ_NAME(idle532mt)
#define MEMINIT __initsbsz532.doj
#define FLT64 RT_LIB_NAME(f64ieee532)
#ifdef IEEEFP
#define FPLIBS RT_LIB_NAME(sftflt532), FLT64, RT_LIB_NAME(dsp532)
#else
#define FPLIBS FLT64, RT_LIB_NAME(dsp532), RT_LIB_NAME(sftflt532)
#endif
#ifdef _DINKUM_IO
#define LIBC RT_LIB_NAME(c532mt), RT_LIB_NAME(rt_fileio532mt), RT_LIB_NAME(io532_mt)
#else
#define LIBC RT_LIB_NAME(io532_mt), RT_LIB_NAME(c532mt)
#endif
$LIBRARIES = RT_LIB_NAME(small532mt), MEMINIT, LIBC, RT_LIB_NAME(m3free532), RT_LIB_NAME(event532mt), RT_LIB_NAME(x532mt), RT_LIB_NAME_EH(cpp532mt), RT_LIB_NAME_EH(cpprt532mt), FPLIBS, libetsi532.dlb, OMEGA,RT_LIB_NAME(drv537), RT_LIB_NAME(ssl537_vdk), RT_LIB_NAME(rt_fileio532mt);
$BASE_LIBRARIES = $LIBRARIES;
#define VDK_LIB_NAME_(x) VDK_LIB_NAME_MACRO_(x)
$LIBS = VDK_LIB_NAME_(CORE), VDK_LIB_NAME_(VDK_IFLAG_), $BASE_LIBRARIES;
$OBJS = CRT, $COMMAND_LINE_OBJECTS, cplbtab537.doj, RT_OBJ_NAME(crtn532);
//
// Memory map.
//
// The known memory spaces are as follows:
//
// 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)
// 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)
// 0xFFB01000 - 0xFFBFFFFF Reserved
// 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)
// 0xFFA14000 - 0xFFAFFFFF Reserved
// 0xFFA10000 - 0XFFA13FFF Code SRAM / cache (16K)
// 0xFFA0C000 - 0xFFA0FFFF Reserved
// 0xFFA08000 - 0xFFA0BFFF Instruction Bank B SRAM (16K)
// 0xFFA00000 - 0xFFA07FFF Instruction Bank A SRAM (32K)
// 0xFF908000 - 0xFF9FFFFF Reserved
// 0xFF904000 - 0xFF907FFF Data Bank B SRAM / cache (16k)
// 0xFF900000 - 0XFF903FFF Data Bank B SRAM (16k)
// 0xFF808000 - 0xFF8FFFFF Reserved
// 0xFF804000 - 0xFF807FFF Data Bank A SRAM / cache (16k)
// 0xFF800000 - 0XFF803FFF Data Bank A SRAM (16k)
// 0xEF000800 - 0xFF800000 Reserved
// 0xEF000000 - 0xFF8007FF Boot ROM (2K)
// 0x20400000 - 0xEEFFFFFF Reserved
// 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB)
// 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB)
// 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB)
// 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB)
// 0x00000000 - 0x1FFFFFFF SDRAM MEMORY (16MB - 512MB)
//
MEMORY
{
mem_l1_scratch { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
mem_l1_code_cache { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }
mem_l1_code { TYPE(RAM) START(0xFFA00000) END(0xFFA0BFFF) WIDTH(8) }
// The mem_EVT sections should be placed in data memory
mem_EVT_all { TYPE(RAM) START(0xFF900000) END(0xFF900003) WIDTH(8) }
mem_EVT_NMI { TYPE(RAM) START(0xFF900004) END(0xFF900007) WIDTH(8) }
mem_EVT_EVX { TYPE(RAM) START(0xFF900008) END(0xFF90000B) WIDTH(8) }
mem_EVT_IRPTEN { TYPE(RAM) START(0xFF90000C) END(0xFF90000F) WIDTH(8) }
mem_EVT_IVHW { TYPE(RAM) START(0xFF900010) END(0xFF900013) WIDTH(8) }
mem_EVT_IVTMR { TYPE(RAM) START(0xFF900014) END(0xFF900017) WIDTH(8) }
mem_EVT_IVG7 { TYPE(RAM) START(0xFF900018) END(0xFF90001B) WIDTH(8) }
mem_EVT_IVG8 { TYPE(RAM) START(0xFF90001C) END(0xFF90001F) WIDTH(8) }
mem_EVT_IVG9 { TYPE(RAM) START(0xFF900020) END(0xFF900023) WIDTH(8) }
mem_EVT_IVG10 { TYPE(RAM) START(0xFF900024) END(0xFF900027) WIDTH(8) }
mem_EVT_IVG11 { TYPE(RAM) START(0xFF900028) END(0xFF90002B) WIDTH(8) }
mem_EVT_IVG12 { TYPE(RAM) START(0xFF90002C) END(0xFF90002F) WIDTH(8) }
mem_EVT_IVG13 { TYPE(RAM) START(0xFF900030) END(0xFF900033) WIDTH(8) }
mem_EVT_IVG14 { TYPE(RAM) START(0xFF900034) END(0xFF900037) WIDTH(8) }
mem_EVT_IVG15 { TYPE(RAM) START(0xFF900038) END(0xFF90003B) WIDTH(8) }
mem_l1_data_b_stack{ TYPE(RAM) START(0xFF90003C) END(0xFF90083B) WIDTH(8) }
#ifdef USE_CACHE
#ifdef __ADI_LIBEH__
mem_l1_data_b { TYPE(RAM) START(0xFF90083C) END(0xFF906FFF) WIDTH(8) }
mem_l1_data_b_cache { TYPE(RAM) START(0xFF907000) END(0xFF907FFF) WIDTH(8) }
#else
mem_l1_data_b { TYPE(RAM) START(0xFF90083C) END(0xFF903FFF) WIDTH(8) }
mem_l1_data_b_cache { TYPE(RAM) START(0xFF904000) END(0xFF907FFF) WIDTH(8) }
#endif
#else
mem_l1_data_b { TYPE(RAM) START(0xFF90083C) END(0xFF907FFF) WIDTH(8) }
#endif /* USE_CACHE */
mem_l1_data_a { TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) }
mem_l1_data_a_cache { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) }
mem_sdram0 { TYPE(RAM) START(0x02000000) END(0x03FFFFFF) WIDTH(8) }
mem_sdram0_heap{ TYPE(RAM) START(0x00000004) END(0x01FFFFFF) WIDTH(8) }
}
PROCESSOR p0
{
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
RESOLVE(start,0xFFA00000)
KEEP(start,_main)
SECTIONS
{
sec_EVT_all { INPUT_SECTIONS( $OBJS( seg_EVT_all ) $LIBS( seg_EVT_all ) ) } > mem_EVT_all
sec_EVT_NMI { INPUT_SECTIONS( $OBJS( seg_EVT_NMI ) $LIBS( seg_EVT_NMI ) ) } > mem_EVT_NMI
sec_EVT_EVX { INPUT_SECTIONS( $OBJS( seg_EVT_EVX ) $LIBS( seg_EVT_EVX ) ) } > mem_EVT_EVX
sec_EVT_IRPTEN { INPUT_SECTIONS( $OBJS( seg_EVT_IRPTEN ) $LIBS( seg_EVT_IRPTEN ) ) } > mem_EVT_IRPTEN
sec_EVT_IVHW { INPUT_SECTIONS( $OBJS( seg_EVT_IVHW ) $LIBS( seg_EVT_IVHW ) ) } > mem_EVT_IVHW
sec_EVT_IVTMR { INPUT_SECTIONS( $OBJS( seg_EVT_IVTMR ) $LIBS( seg_EVT_IVTMR ) ) } > mem_EVT_IVTMR
sec_EVT_IVG7 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG7 ) $LIBS( seg_EVT_IVG7 ) ) } > mem_EVT_IVG7
sec_EVT_IVG8 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG8 ) $LIBS( seg_EVT_IVG8 ) ) } > mem_EVT_IVG8
sec_EVT_IVG9 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG9 ) $LIBS( seg_EVT_IVG9 ) ) } > mem_EVT_IVG9
sec_EVT_IVG10 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG10 ) $LIBS( seg_EVT_IVG10 ) ) } > mem_EVT_IVG10
sec_EVT_IVG11 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG11 ) $LIBS( seg_EVT_IVG11 ) ) } > mem_EVT_IVG11
sec_EVT_IVG12 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG12 ) $LIBS( seg_EVT_IVG12 ) ) } > mem_EVT_IVG12
sec_EVT_IVG13 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG13 ) $LIBS( seg_EVT_IVG13 ) ) } > mem_EVT_IVG13
sec_EVT_IVG14 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG14 ) $LIBS( seg_EVT_IVG14 ) ) } > mem_EVT_IVG14
sec_EVT_IVG15 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG15 ) $LIBS( seg_EVT_IVG15 ) ) } > mem_EVT_IVG15
sec_program
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $LIBS(VDK_ISR_code) )
INPUT_SECTIONS( $OBJS(L1_code) $LIBS(L1_code))
INPUT_SECTIONS( $OBJS(cplb_code) $LIBS(cplb_code))
INPUT_SECTIONS( $OBJS(cplb) $LIBS(cplb))
INPUT_SECTIONS( $OBJS(noncache_code) $LIBS(noncache_code))
INPUT_SECTIONS( $OBJS(program) $LIBS(program) )
} >mem_l1_code
#ifndef USE_CACHE
l1_code
{
INPUT_SECTION_ALIGN(4)
___l1_code_cache = 0;
INPUT_SECTIONS( $LIBS(VDK_ISR_code) )
INPUT_SECTIONS( $OBJS(L1_code) $LIBS(L1_code))
INPUT_SECTIONS( $OBJS(cplb_code) $LIBS(cplb_code))
INPUT_SECTIONS( $OBJS(cplb) $LIBS(cplb))
INPUT_SECTIONS( $OBJS(program) $LIBS(program))
} >mem_l1_code_cache
#endif /* USE_CACHE */
data_L1_data_a
{
INPUT_SECTION_ALIGN(4)
#ifndef USE_CACHE
___l1_data_cache_a = 0;
#endif
INPUT_SECTIONS( $OBJS(L1_data_a) $LIBS(L1_data_a))
INPUT_SECTIONS( $OBJS(vtbl) $LIBS(vtbl) )
INPUT_SECTIONS( $OBJS(.frt) $LIBS(.frt) )
INPUT_SECTIONS( $OBJS(.frtl) $LIBS(.frtl) )
INPUT_SECTIONS( $OBJS(ctor) $LIBS(ctor) )
INPUT_SECTIONS( $OBJS(ctorl) $LIBS(ctorl) )
INPUT_SECTIONS( $OBJS(.gdt) $LIBS(.gdt) )
INPUT_SECTIONS( $OBJS(.gdtl) $LIBS(.gdtl) )
INPUT_SECTIONS( $OBJS(.edt) $LIBS(.edt) )
INPUT_SECTIONS( $OBJS(.cht) $LIBS(.cht) )
INPUT_SECTIONS( $OBJS(cplb_data) $LIBS(cplb_data))
INPUT_SECTIONS($OBJS(data1) $LIBS(data1))
INPUT_SECTIONS($OBJS(voldata) $LIBS(voldata))
} >mem_l1_data_a
constdata_L1_data_a
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJS(constdata) $LIBS(constdata))
} >mem_l1_data_a
bsz_L1_data_a ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz) $LIBS(bsz))
} >mem_l1_data_a
data_L1_data_b
{
INPUT_SECTION_ALIGN(4)
#ifndef USE_CACHE
___l1_data_cache_b = 0;
#endif
INPUT_SECTIONS( $OBJS(L1_data_b) $LIBS(L1_data_b))
INPUT_SECTIONS( $OBJS(bsz_init) $LIBS(bsz_init))
INPUT_SECTIONS( $OBJS(.edt) $LIBS(.edt) )
INPUT_SECTIONS( $OBJS(.cht) $LIBS(.cht) )
INPUT_SECTIONS( $OBJS(cplb_data) $LIBS(cplb_data))
INPUT_SECTIONS($OBJS(data1) $LIBS(data1))
INPUT_SECTIONS($OBJS(voldata) $LIBS(voldata))
} >mem_l1_data_b
.meminit { ALIGN(4) } >mem_l1_data_b
constdata_L1_data_b
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJS(constdata) $LIBS(constdata))
} >mem_l1_data_b
bsz_L1_data_b ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz) $LIBS(bsz))
} >mem_l1_data_b
#ifdef USE_CACHE
l1_code
{
INPUT_SECTION_ALIGN(4)
___l1_code_cache = 1;
} >mem_l1_code_cache
l1_data_a_cache
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_a = 1;
} >mem_l1_data_a_cache
l1_data_b_cache
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_b = 1;
} >mem_l1_data_b_cache
#endif /* } USE_CACHE */
stack
{
ldf_stack_space = .;
ldf_stack_end = ldf_stack_space + MEMORY_SIZEOF(mem_l1_data_b_stack);
} >mem_l1_data_b_stack
#if defined(USE_CACHE) || defined(USE_SDRAM)
heap
{
// Allocate a heap for the application
ldf_heap_space = .;
ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(mem_sdram0_heap) - 1;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} >mem_sdram0_heap
#else
heap
{
// Allocate a heap for the application
ldf_heap_space = .;
ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(mem_l1_data_a_cache) - 1;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} >mem_l1_data_a_cache
#endif /* USE_CACHE } */
sdram
{
#if defined(USE_CACHE) || defined(USE_SDRAM)
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(sdram0) $LIBS(sdram0))
INPUT_SECTIONS( $OBJS(noncache_code) $LIBS(noncache_code))
INPUT_SECTIONS( $OBJS(program) $LIBS(program))
INPUT_SECTIONS( $OBJS(cplb) $LIBS(cplb))
INPUT_SECTIONS( $OBJS(cplb_code) $LIBS(cplb_code))
INPUT_SECTIONS($OBJS(data1) $LIBS(data1))
INPUT_SECTIONS($OBJS(voldata) $LIBS(voldata))
INPUT_SECTIONS($OBJS(constdata) $LIBS(constdata))
INPUT_SECTIONS( $OBJS(cplb_data) $LIBS(cplb_data))
#endif /* USE_CACHE } */
} >mem_sdram0
#if defined(USE_CACHE) || defined(USE_SDRAM)
bsz_sdram0 ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz) $LIBS(bsz))
} >mem_sdram0
#endif /* USE_CACHE */
}
}
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