📄 at91rm9200_sys.h
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#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock#define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK4RDY (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------// *****************************************************************************// SOFTWARE API DEFINITION FOR Clock Generator Controler// *****************************************************************************// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable#define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier#define AT91C_CKGR_USB_96M (0x1 << 28) // (CKGR) Divider for USB Ports#define AT91C_CKGR_USB_PLL (0x1 << 29) // (CKGR) PLL Use// *****************************************************************************// SOFTWARE API DEFINITION FOR Debug Unit// *****************************************************************************// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------#define AT91C_DBGU_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt#define AT91C_DBGU_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------#define AT91C_DBGU_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG// *****************************************************************************// SOFTWARE API DEFINITION FOR Peripheral Data Controller// *****************************************************************************// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------// *****************************************************************************// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller// *****************************************************************************// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask// *****************************************************************************// SOFTWARE API DEFINITION FOR External Bus Interface// *****************************************************************************// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register --------#define AT91C_EBI_CS0A (0x1 << 0) // (EBI) Chip Select 0 Assignment#define AT91C_EBI_CS0A_SMC (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.#define AT91C_EBI_CS0A_BFC (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.#define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.#define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.#define AT91C_EBI_CS3A_SMC_SmartMedia (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.#define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register --------#define AT91C_EBI_DBPUC (0x1 << 0) // (EBI) Data Bus Pull-Up Configuration#define AT91C_EBI_EBSEN (0x1 << 1) // (EBI) Bus Sharing Enable// *****************************************************************************// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface// *****************************************************************************// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------#define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States#define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable#define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time#define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width#define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit.#define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit.#define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol#define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup#define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.#define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.#define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.#define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.#define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time#define AT91C_SMC2_RWHOLD (0x7 << 29) // (SMC2) Read and Write Signal Hold Time// *****************************************************************************// SOFTWARE API DEFINITION FOR SDRAM Controller Interface// *****************************************************************************// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register --------#define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode#define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode#define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command#define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command#define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command#define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command#define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width#define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus#define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register --------#define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register --------#define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits#define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits#define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits#define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits#define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits#define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits#define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits#define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits#define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits#define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks#define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks#define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks#define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency#define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles#define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles#define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles#define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles#define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles#define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles#define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register --------#define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register --------#define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------#define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register --------// *****************************************************************************// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface// *****************************************************************************// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register --------#define AT91C_BFC_BFCOM (0x3 << 0) // (BFC) Burst Flash Controller Operating Mode#define AT91C_BFC_BFCOM_DISABLED (0x0) // (BFC) NPCS0 is driven by the SMC or remains high.#define AT91C_BFC_BFCOM_ASYNC (0x1) // (BFC) Asynchronous#define AT91C_BFC_BFCOM_BURST_READ (0x2) // (BFC) Burst Read#define AT91C_BFC_BFCC (0x3 << 2) // (BFC) Burst Flash Controller Operating Mode#define AT91C_BFC_BFCC_MCK (0x1 << 2) // (BFC) Master Clock.#define AT91C_BFC_BFCC_MCK_DIV_2 (0x2 << 2) // (BFC) Master Clock divided by 2.#define AT91C_BFC_BFCC_MCK_DIV_4 (0x3 << 2) // (BFC) Master Clock divided by 4.#define AT91C_BFC_AVL (0xF << 4) // (BFC) Address Valid Latency#define AT91C_BFC_PAGES (0x7 << 8) // (BFC) Page Size#define AT91C_BFC_PAGES_NO_PAGE (0x0 << 8) // (BFC) No page handling.#define AT91C_BFC_PAGES_16 (0x1 << 8) // (BFC) 16 bytes page size.#define AT91C_BFC_PAGES_32 (0x2 << 8) // (BFC) 32 bytes page size.#define AT91C_BFC_PAGES_64 (0x3 << 8) // (BFC) 64 bytes page size.#define AT91C_BFC_PAGES_128 (0x4 << 8) // (BFC) 128 bytes page size.#define AT91C_BFC_PAGES_256 (0x5 << 8) // (BFC) 256 bytes page size.#define AT91C_BFC_PAGES_512 (0x6 << 8) // (BFC) 512 bytes page size.#define AT91C_BFC_PAGES_1024 (0x7 << 8) // (BFC) 1024 bytes page size.#define AT91C_BFC_OEL (0x3 << 12) // (BFC) Output Enable Latency#define AT91C_BFC_BAAEN (0x1 << 16) // (BFC) Burst Address Advance Enable#define AT91C_BFC_BFOEH (0x1 << 17) // (BFC) Burst Flash Output Enable Handling#define AT91C_BFC_MUXEN (0x1 << 18) // (BFC) Multiplexed Bus Enable#define AT91C_BFC_RDYEN (0x1 << 19) // (BFC) Ready Enable Mode#endif⌨️ 快捷键说明
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