📄 at91rm9200_sys.h
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AT91_REG ST_IDR; // Interrupt Disable Register AT91_REG ST_IMR; // Interrupt Mask Register AT91_REG ST_RTAR; // Real-time Alarm Register AT91_REG ST_CRTR; // Current Real-time Register AT91_REG Reserved38[54]; // AT91_REG RTC_CR; // Control Register AT91_REG RTC_MR; // Mode Register AT91_REG RTC_TIMR; // Time Register AT91_REG RTC_CALR; // Calendar Register AT91_REG RTC_TIMALR; // Time Alarm Register AT91_REG RTC_CALALR; // Calendar Alarm Register AT91_REG RTC_SR; // Status Register AT91_REG RTC_SCCR; // Status Clear Command Register AT91_REG RTC_IER; // Interrupt Enable Register AT91_REG RTC_IDR; // Interrupt Disable Register AT91_REG RTC_IMR; // Interrupt Mask Register AT91_REG RTC_VER; // Valid Entry Register AT91_REG Reserved39[52]; // AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register AT91_REG Reserved40[1]; // AT91_REG MC_PUIA[16]; // MC Protection Unit Area AT91_REG MC_PUP; // MC Protection Unit Peripherals AT91_REG MC_PUER; // MC Protection Unit Enable Register AT91_REG Reserved41[2]; // AT91_REG EBI_CSA; // Chip Select Assignment Register AT91_REG EBI_CFGR; // Configuration Register AT91_REG Reserved42[2]; // AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG Reserved43[3]; // AT91_REG EBI_BFC_MR; // BFC Mode Register} AT91S_SYS, *AT91PS_SYS;#else/* Offsets from AT91C_BASE_SYS */#define AIC_SMR (0) // Source Mode Register#define AIC_SVR (128) // Source Vector Register#define AIC_IVR (256) // IRQ Vector Register#define AIC_FVR (260) // FIQ Vector Register#define AIC_ISR (264) // Interrupt Status Register#define AIC_IPR (268) // Interrupt Pending Register#define AIC_IMR (272) // Interrupt Mask Register#define AIC_CISR (276) // Core Interrupt Status Register#define AIC_IECR (288) // Interrupt Enable Command Register#define AIC_IDCR (292) // Interrupt Disable Command Register#define AIC_ICCR (296) // Interrupt Clear Command Register#define AIC_ISCR (300) // Interrupt Set Command Register#define AIC_EOICR (304) // End of Interrupt Command Register#define AIC_SPU (308) // Spurious Vector Register#define AIC_DCR (312) // Debug Control Register (Protect)#define AIC_FFER (320) // Fast Forcing Enable Register#define AIC_FFDR (324) // Fast Forcing Disable Register#define AIC_FFSR (328) // Fast Forcing Status Register/* Offsets from AT91C_BASE_SYS */#define DBGU_CR (0x200 + 0) // Control Register#define DBGU_MR (0x200 + 4) // Mode Register#define DBGU_IER (0x200 + 8) // Interrupt Enable Register#define DBGU_IDR (0x200 + 12) // Interrupt Disable Register#define DBGU_IMR (0x200 + 16) // Interrupt Mask Register#define DBGU_CSR (0x200 + 20) // Channel Status Register#define DBGU_RHR (0x200 + 24) // Receiver Holding Register#define DBGU_THR (0x200 + 28) // Transmitter Holding Register#define DBGU_BRGR (0x200 + 32) // Baud Rate Generator Register#define DBGU_C1R (0x200 + 64) // Chip ID1 Register#define DBGU_C2R (0x200 + 68) // Chip ID2 Register#define DBGU_FNTR (0x200 + 72) // Force NTRST Register#define DBGU_RPR (0x200 + 256) // Receive Pointer Register#define DBGU_RCR (0x200 + 260) // Receive Counter Register#define DBGU_TPR (0x200 + 264) // Transmit Pointer Register#define DBGU_TCR (0x200 + 268) // Transmit Counter Register#define DBGU_RNPR (0x200 + 272) // Receive Next Pointer Register#define DBGU_RNCR (0x200 + 276) // Receive Next Counter Register#define DBGU_TNPR (0x200 + 280) // Transmit Next Pointer Register#define DBGU_TNCR (0x200 + 284) // Transmit Next Counter Register#define DBGU_PTCR (0x200 + 288) // PDC Transfer Control Register#define DBGU_PTSR (0x200 + 292) // PDC Transfer Status Register#endif // __ASSEMBLY// *****************************************************************************// SOFTWARE API DEFINITION FOR Memory Controller Interface// *****************************************************************************// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit// *****************************************************************************// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface// *****************************************************************************// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------#define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register#define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register#define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection#define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change.#define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change.#define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight.#define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon.#define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection#define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).#define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).#define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------#define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------#define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second#define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute#define AT91C_RTC_HOUR (0x3F << 16) // (RTC) Current Hour#define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------#define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century#define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year#define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month#define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day#define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register --------#define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable#define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm#define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------#define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable#define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------#define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update#define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag#define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event#define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event#define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register --------// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------#define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time#define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar#define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm#define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm// *****************************************************************************// SOFTWARE API DEFINITION FOR System Timer Interface// *****************************************************************************// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register --------#define AT91C_ST_WDRST (0x1 << 0) // (ST) Watchdog Timer Restart// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register --------#define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register --------#define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart#define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable#define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register --------#define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register --------#define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt#define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow#define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment#define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register --------// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register --------// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register --------// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register --------#define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register --------#define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value// *****************************************************************************// SOFTWARE API DEFINITION FOR Power Management Controler// *****************************************************************************// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock#define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock#define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend#define AT91C_PMC_UHP (0x1 << 4) // (PMC) USB Host Port Clock#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK4 (0x1 << 12) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------⌨️ 快捷键说明
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