shub_mmr_t.h

linux-2.4.29操作系统的源码

#ifdef LITTLE_ENDIAN
typedef union sh_proc2_err_int_enable_u {
	mmr_t	sh_proc2_err_int_enable_regval;
	struct {
		mmr_t	proc2_err_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc2_err_int_enable_s;
} sh_proc2_err_int_enable_u_t;
#else
typedef union sh_proc2_err_int_enable_u {
	mmr_t	sh_proc2_err_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc2_err_enable : 1;
	} sh_proc2_err_int_enable_s;
} sh_proc2_err_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC3_ERR_INT_ENABLE"                  */
/*          SHub Processor 3 Error Interrupt Enable Registers           */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc3_err_int_enable_u {
	mmr_t	sh_proc3_err_int_enable_regval;
	struct {
		mmr_t	proc3_err_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc3_err_int_enable_s;
} sh_proc3_err_int_enable_u_t;
#else
typedef union sh_proc3_err_int_enable_u {
	mmr_t	sh_proc3_err_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc3_err_enable : 1;
	} sh_proc3_err_int_enable_s;
} sh_proc3_err_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC0_ADV_INT_ENABLE"                  */
/*         SHub Processor 0 Advisory Interrupt Enable Registers         */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc0_adv_int_enable_u {
	mmr_t	sh_proc0_adv_int_enable_regval;
	struct {
		mmr_t	proc0_adv_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc0_adv_int_enable_s;
} sh_proc0_adv_int_enable_u_t;
#else
typedef union sh_proc0_adv_int_enable_u {
	mmr_t	sh_proc0_adv_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc0_adv_enable : 1;
	} sh_proc0_adv_int_enable_s;
} sh_proc0_adv_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC1_ADV_INT_ENABLE"                  */
/*         SHub Processor 1 Advisory Interrupt Enable Registers         */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc1_adv_int_enable_u {
	mmr_t	sh_proc1_adv_int_enable_regval;
	struct {
		mmr_t	proc1_adv_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc1_adv_int_enable_s;
} sh_proc1_adv_int_enable_u_t;
#else
typedef union sh_proc1_adv_int_enable_u {
	mmr_t	sh_proc1_adv_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc1_adv_enable : 1;
	} sh_proc1_adv_int_enable_s;
} sh_proc1_adv_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC2_ADV_INT_ENABLE"                  */
/*         SHub Processor 2 Advisory Interrupt Enable Registers         */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc2_adv_int_enable_u {
	mmr_t	sh_proc2_adv_int_enable_regval;
	struct {
		mmr_t	proc2_adv_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc2_adv_int_enable_s;
} sh_proc2_adv_int_enable_u_t;
#else
typedef union sh_proc2_adv_int_enable_u {
	mmr_t	sh_proc2_adv_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc2_adv_enable : 1;
	} sh_proc2_adv_int_enable_s;
} sh_proc2_adv_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC3_ADV_INT_ENABLE"                  */
/*         SHub Processor 3 Advisory Interrupt Enable Registers         */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc3_adv_int_enable_u {
	mmr_t	sh_proc3_adv_int_enable_regval;
	struct {
		mmr_t	proc3_adv_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc3_adv_int_enable_s;
} sh_proc3_adv_int_enable_u_t;
#else
typedef union sh_proc3_adv_int_enable_u {
	mmr_t	sh_proc3_adv_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc3_adv_enable : 1;
	} sh_proc3_adv_int_enable_s;
} sh_proc3_adv_int_enable_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_PROFILE_INT_CONFIG"                   */
/*            SHub Profile Interrupt Configuration Registers            */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_profile_int_config_u {
	mmr_t	sh_profile_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_profile_int_config_s;
} sh_profile_int_config_u_t;
#else
typedef union sh_profile_int_config_u {
	mmr_t	sh_profile_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_profile_int_config_s;
} sh_profile_int_config_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_PROFILE_INT_ENABLE"                   */
/*               SHub Profile Interrupt Enable Registers                */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_profile_int_enable_u {
	mmr_t	sh_profile_int_enable_regval;
	struct {
		mmr_t	profile_enable : 1;
		mmr_t	reserved_0     : 63;
	} sh_profile_int_enable_s;
} sh_profile_int_enable_u_t;
#else
typedef union sh_profile_int_enable_u {
	mmr_t	sh_profile_int_enable_regval;
	struct {
		mmr_t	reserved_0     : 63;
		mmr_t	profile_enable : 1;
	} sh_profile_int_enable_s;
} sh_profile_int_enable_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC0_INT_CONFIG"                     */
/*                SHub RTC 0 Interrupt Config Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc0_int_config_u {
	mmr_t	sh_rtc0_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_rtc0_int_config_s;
} sh_rtc0_int_config_u_t;
#else
typedef union sh_rtc0_int_config_u {
	mmr_t	sh_rtc0_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_rtc0_int_config_s;
} sh_rtc0_int_config_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC0_INT_ENABLE"                     */
/*                SHub RTC 0 Interrupt Enable Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc0_int_enable_u {
	mmr_t	sh_rtc0_int_enable_regval;
	struct {
		mmr_t	rtc0_enable : 1;
		mmr_t	reserved_0  : 63;
	} sh_rtc0_int_enable_s;
} sh_rtc0_int_enable_u_t;
#else
typedef union sh_rtc0_int_enable_u {
	mmr_t	sh_rtc0_int_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	rtc0_enable : 1;
	} sh_rtc0_int_enable_s;
} sh_rtc0_int_enable_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC1_INT_CONFIG"                     */
/*                SHub RTC 1 Interrupt Config Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc1_int_config_u {
	mmr_t	sh_rtc1_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_rtc1_int_config_s;
} sh_rtc1_int_config_u_t;
#else
typedef union sh_rtc1_int_config_u {
	mmr_t	sh_rtc1_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_rtc1_int_config_s;
} sh_rtc1_int_config_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC1_INT_ENABLE"                     */
/*                SHub RTC 1 Interrupt Enable Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc1_int_enable_u {
	mmr_t	sh_rtc1_int_enable_regval;
	struct {
		mmr_t	rtc1_enable : 1;
		mmr_t	reserved_0  : 63;
	} sh_rtc1_int_enable_s;
} sh_rtc1_int_enable_u_t;
#else
typedef union sh_rtc1_int_enable_u {
	mmr_t	sh_rtc1_int_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	rtc1_enable : 1;
	} sh_rtc1_int_enable_s;
} sh_rtc1_int_enable_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC2_INT_CONFIG"                     */
/*                SHub RTC 2 Interrupt Config Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc2_int_config_u {
	mmr_t	sh_rtc2_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_rtc2_int_config_s;
} sh_rtc2_int_config_u_t;
#else
typedef union sh_rtc2_int_config_u {
	mmr_t	sh_rtc2_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_rtc2_int_config_s;
} sh_rtc2_int_config_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC2_INT_ENABLE"                     */
/*                SHub RTC 2 Interrupt Enable Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc2_int_enable_u {
	mmr_t	sh_rtc2_int_enable_regval;
	struct {
		mmr_t	rtc2_enable : 1;
		mmr_t	reserved_0  : 63;
	} sh_rtc2_int_enable_s;
} sh_rtc2_int_enable_u_t;
#else
typedef union sh_rtc2_int_enable_u {
	mmr_t	sh_rtc2_int_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	rtc2_enable : 1;
	} sh_rtc2_int_enable_s;
} sh_rtc2_int_enable_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC3_INT_CONFIG"                     */
/*                SHub RTC 3 Interrupt Config Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc3_int_config_u {
	mmr_t	sh_rtc3_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_rtc3_int_config_s;
} sh_rtc3_int_config_u_t;
#else
typedef union sh_rtc3_int_config_u {
	mmr_t	sh_rtc3_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_rtc3_int_config_s;
} sh_rtc3_int_config_u_t;
#endif

/* ==================================================================== */
/*                    Register "SH_RTC3_INT_ENABLE"                     */
/*                SHub RTC 3 Interrupt Enable Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_rtc3_int_enable_u {
	mmr_t	sh_rtc3_int_enable_regval;
	struct {
		mmr_t	rtc3_enable : 1;
		mmr_t	reserved_0  : 63;
	} sh_rtc3_int_enable_s;
} sh_rtc3_int_enable_u_t;
#else
typedef union sh_rtc3_int_enable_u {
	mmr_t	sh_rtc3_int_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	rtc3_enable : 1