shub_mmr_t.h

linux-2.4.29操作系统的源码

	} sh_local_int4_enable_s;
} sh_local_int4_enable_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_LOCAL_INT5_CONFIG"                    */
/*                   SHub Local Interrupt 5 Registers                   */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_local_int5_config_u {
	mmr_t	sh_local_int5_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_local_int5_config_s;
} sh_local_int5_config_u_t;
#else
typedef union sh_local_int5_config_u {
	mmr_t	sh_local_int5_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_local_int5_config_s;
} sh_local_int5_config_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_LOCAL_INT5_ENABLE"                    */
/*                    SHub Local Interrupt 5 Enable                     */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_local_int5_enable_u {
	mmr_t	sh_local_int5_enable_regval;
	struct {
		mmr_t	pi_hw_int           : 1;
		mmr_t	md_hw_int           : 1;
		mmr_t	xn_hw_int           : 1;
		mmr_t	lb_hw_int           : 1;
		mmr_t	ii_hw_int           : 1;
		mmr_t	pi_ce_int           : 1;
		mmr_t	md_ce_int           : 1;
		mmr_t	xn_ce_int           : 1;
		mmr_t	pi_uce_int          : 1;
		mmr_t	md_uce_int          : 1;
		mmr_t	xn_uce_int          : 1;
		mmr_t	reserved_0          : 1;
		mmr_t	system_shutdown_int : 1;
		mmr_t	uart_int            : 1;
		mmr_t	l1_nmi_int          : 1;
		mmr_t	stop_clock          : 1;
		mmr_t	reserved_1          : 48;
	} sh_local_int5_enable_s;
} sh_local_int5_enable_u_t;
#else
typedef union sh_local_int5_enable_u {
	mmr_t	sh_local_int5_enable_regval;
	struct {
		mmr_t	reserved_1          : 48;
		mmr_t	stop_clock          : 1;
		mmr_t	l1_nmi_int          : 1;
		mmr_t	uart_int            : 1;
		mmr_t	system_shutdown_int : 1;
		mmr_t	reserved_0          : 1;
		mmr_t	xn_uce_int          : 1;
		mmr_t	md_uce_int          : 1;
		mmr_t	pi_uce_int          : 1;
		mmr_t	xn_ce_int           : 1;
		mmr_t	md_ce_int           : 1;
		mmr_t	pi_ce_int           : 1;
		mmr_t	ii_hw_int           : 1;
		mmr_t	lb_hw_int           : 1;
		mmr_t	xn_hw_int           : 1;
		mmr_t	md_hw_int           : 1;
		mmr_t	pi_hw_int           : 1;
	} sh_local_int5_enable_s;
} sh_local_int5_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC0_ERR_INT_CONFIG"                  */
/*              SHub Processor 0 Error Interrupt Registers              */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc0_err_int_config_u {
	mmr_t	sh_proc0_err_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc0_err_int_config_s;
} sh_proc0_err_int_config_u_t;
#else
typedef union sh_proc0_err_int_config_u {
	mmr_t	sh_proc0_err_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc0_err_int_config_s;
} sh_proc0_err_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC1_ERR_INT_CONFIG"                  */
/*              SHub Processor 1 Error Interrupt Registers              */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc1_err_int_config_u {
	mmr_t	sh_proc1_err_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc1_err_int_config_s;
} sh_proc1_err_int_config_u_t;
#else
typedef union sh_proc1_err_int_config_u {
	mmr_t	sh_proc1_err_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc1_err_int_config_s;
} sh_proc1_err_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC2_ERR_INT_CONFIG"                  */
/*              SHub Processor 2 Error Interrupt Registers              */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc2_err_int_config_u {
	mmr_t	sh_proc2_err_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc2_err_int_config_s;
} sh_proc2_err_int_config_u_t;
#else
typedef union sh_proc2_err_int_config_u {
	mmr_t	sh_proc2_err_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc2_err_int_config_s;
} sh_proc2_err_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC3_ERR_INT_CONFIG"                  */
/*              SHub Processor 3 Error Interrupt Registers              */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc3_err_int_config_u {
	mmr_t	sh_proc3_err_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc3_err_int_config_s;
} sh_proc3_err_int_config_u_t;
#else
typedef union sh_proc3_err_int_config_u {
	mmr_t	sh_proc3_err_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc3_err_int_config_s;
} sh_proc3_err_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC0_ADV_INT_CONFIG"                  */
/*            SHub Processor 0 Advisory Interrupt Registers             */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc0_adv_int_config_u {
	mmr_t	sh_proc0_adv_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc0_adv_int_config_s;
} sh_proc0_adv_int_config_u_t;
#else
typedef union sh_proc0_adv_int_config_u {
	mmr_t	sh_proc0_adv_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc0_adv_int_config_s;
} sh_proc0_adv_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC1_ADV_INT_CONFIG"                  */
/*            SHub Processor 1 Advisory Interrupt Registers             */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc1_adv_int_config_u {
	mmr_t	sh_proc1_adv_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc1_adv_int_config_s;
} sh_proc1_adv_int_config_u_t;
#else
typedef union sh_proc1_adv_int_config_u {
	mmr_t	sh_proc1_adv_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc1_adv_int_config_s;
} sh_proc1_adv_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC2_ADV_INT_CONFIG"                  */
/*            SHub Processor 2 Advisory Interrupt Registers             */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc2_adv_int_config_u {
	mmr_t	sh_proc2_adv_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc2_adv_int_config_s;
} sh_proc2_adv_int_config_u_t;
#else
typedef union sh_proc2_adv_int_config_u {
	mmr_t	sh_proc2_adv_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc2_adv_int_config_s;
} sh_proc2_adv_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC3_ADV_INT_CONFIG"                  */
/*            SHub Processor 3 Advisory Interrupt Registers             */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc3_adv_int_config_u {
	mmr_t	sh_proc3_adv_int_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 4;
	} sh_proc3_adv_int_config_s;
} sh_proc3_adv_int_config_u_t;
#else
typedef union sh_proc3_adv_int_config_u {
	mmr_t	sh_proc3_adv_int_config_regval;
	struct {
		mmr_t	reserved_2  : 4;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_proc3_adv_int_config_s;
} sh_proc3_adv_int_config_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC0_ERR_INT_ENABLE"                  */
/*          SHub Processor 0 Error Interrupt Enable Registers           */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc0_err_int_enable_u {
	mmr_t	sh_proc0_err_int_enable_regval;
	struct {
		mmr_t	proc0_err_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc0_err_int_enable_s;
} sh_proc0_err_int_enable_u_t;
#else
typedef union sh_proc0_err_int_enable_u {
	mmr_t	sh_proc0_err_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc0_err_enable : 1;
	} sh_proc0_err_int_enable_s;
} sh_proc0_err_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC1_ERR_INT_ENABLE"                  */
/*          SHub Processor 1 Error Interrupt Enable Registers           */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_proc1_err_int_enable_u {
	mmr_t	sh_proc1_err_int_enable_regval;
	struct {
		mmr_t	proc1_err_enable : 1;
		mmr_t	reserved_0       : 63;
	} sh_proc1_err_int_enable_s;
} sh_proc1_err_int_enable_u_t;
#else
typedef union sh_proc1_err_int_enable_u {
	mmr_t	sh_proc1_err_int_enable_regval;
	struct {
		mmr_t	reserved_0       : 63;
		mmr_t	proc1_err_enable : 1;
	} sh_proc1_err_int_enable_s;
} sh_proc1_err_int_enable_u_t;
#endif

/* ==================================================================== */
/*                  Register "SH_PROC2_ERR_INT_ENABLE"                  */
/*          SHub Processor 2 Error Interrupt Enable Registers           */
/* ==================================================================== */