📄 shub_mmr_t.h
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mmr_t base : 29; mmr_t reserved_1 : 2; mmr_t idx : 8; mmr_t reserved_2 : 4; } sh_local_int0_config_s;} sh_local_int0_config_u_t;#elsetypedef union sh_local_int0_config_u { mmr_t sh_local_int0_config_regval; struct { mmr_t reserved_2 : 4; mmr_t idx : 8; mmr_t reserved_1 : 2; mmr_t base : 29; mmr_t reserved_0 : 1; mmr_t pid : 16; mmr_t agt : 1; mmr_t type : 3; } sh_local_int0_config_s;} sh_local_int0_config_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT0_ENABLE" *//* SHub Local Interrupt 0 Enable *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int0_enable_u { mmr_t sh_local_int0_enable_regval; struct { mmr_t pi_hw_int : 1; mmr_t md_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t ii_hw_int : 1; mmr_t pi_ce_int : 1; mmr_t md_ce_int : 1; mmr_t xn_ce_int : 1; mmr_t pi_uce_int : 1; mmr_t md_uce_int : 1; mmr_t xn_uce_int : 1; mmr_t reserved_0 : 1; mmr_t system_shutdown_int : 1; mmr_t uart_int : 1; mmr_t l1_nmi_int : 1; mmr_t stop_clock : 1; mmr_t reserved_1 : 48; } sh_local_int0_enable_s;} sh_local_int0_enable_u_t;#elsetypedef union sh_local_int0_enable_u { mmr_t sh_local_int0_enable_regval; struct { mmr_t reserved_1 : 48; mmr_t stop_clock : 1; mmr_t l1_nmi_int : 1; mmr_t uart_int : 1; mmr_t system_shutdown_int : 1; mmr_t reserved_0 : 1; mmr_t xn_uce_int : 1; mmr_t md_uce_int : 1; mmr_t pi_uce_int : 1; mmr_t xn_ce_int : 1; mmr_t md_ce_int : 1; mmr_t pi_ce_int : 1; mmr_t ii_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t md_hw_int : 1; mmr_t pi_hw_int : 1; } sh_local_int0_enable_s;} sh_local_int0_enable_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT1_CONFIG" *//* SHub Local Interrupt 1 Registers *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int1_config_u { mmr_t sh_local_int1_config_regval; struct { mmr_t type : 3; mmr_t agt : 1; mmr_t pid : 16; mmr_t reserved_0 : 1; mmr_t base : 29; mmr_t reserved_1 : 2; mmr_t idx : 8; mmr_t reserved_2 : 4; } sh_local_int1_config_s;} sh_local_int1_config_u_t;#elsetypedef union sh_local_int1_config_u { mmr_t sh_local_int1_config_regval; struct { mmr_t reserved_2 : 4; mmr_t idx : 8; mmr_t reserved_1 : 2; mmr_t base : 29; mmr_t reserved_0 : 1; mmr_t pid : 16; mmr_t agt : 1; mmr_t type : 3; } sh_local_int1_config_s;} sh_local_int1_config_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT1_ENABLE" *//* SHub Local Interrupt 1 Enable *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int1_enable_u { mmr_t sh_local_int1_enable_regval; struct { mmr_t pi_hw_int : 1; mmr_t md_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t ii_hw_int : 1; mmr_t pi_ce_int : 1; mmr_t md_ce_int : 1; mmr_t xn_ce_int : 1; mmr_t pi_uce_int : 1; mmr_t md_uce_int : 1; mmr_t xn_uce_int : 1; mmr_t reserved_0 : 1; mmr_t system_shutdown_int : 1; mmr_t uart_int : 1; mmr_t l1_nmi_int : 1; mmr_t stop_clock : 1; mmr_t reserved_1 : 48; } sh_local_int1_enable_s;} sh_local_int1_enable_u_t;#elsetypedef union sh_local_int1_enable_u { mmr_t sh_local_int1_enable_regval; struct { mmr_t reserved_1 : 48; mmr_t stop_clock : 1; mmr_t l1_nmi_int : 1; mmr_t uart_int : 1; mmr_t system_shutdown_int : 1; mmr_t reserved_0 : 1; mmr_t xn_uce_int : 1; mmr_t md_uce_int : 1; mmr_t pi_uce_int : 1; mmr_t xn_ce_int : 1; mmr_t md_ce_int : 1; mmr_t pi_ce_int : 1; mmr_t ii_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t md_hw_int : 1; mmr_t pi_hw_int : 1; } sh_local_int1_enable_s;} sh_local_int1_enable_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT2_CONFIG" *//* SHub Local Interrupt 2 Registers *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int2_config_u { mmr_t sh_local_int2_config_regval; struct { mmr_t type : 3; mmr_t agt : 1; mmr_t pid : 16; mmr_t reserved_0 : 1; mmr_t base : 29; mmr_t reserved_1 : 2; mmr_t idx : 8; mmr_t reserved_2 : 4; } sh_local_int2_config_s;} sh_local_int2_config_u_t;#elsetypedef union sh_local_int2_config_u { mmr_t sh_local_int2_config_regval; struct { mmr_t reserved_2 : 4; mmr_t idx : 8; mmr_t reserved_1 : 2; mmr_t base : 29; mmr_t reserved_0 : 1; mmr_t pid : 16; mmr_t agt : 1; mmr_t type : 3; } sh_local_int2_config_s;} sh_local_int2_config_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT2_ENABLE" *//* SHub Local Interrupt 2 Enable *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int2_enable_u { mmr_t sh_local_int2_enable_regval; struct { mmr_t pi_hw_int : 1; mmr_t md_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t ii_hw_int : 1; mmr_t pi_ce_int : 1; mmr_t md_ce_int : 1; mmr_t xn_ce_int : 1; mmr_t pi_uce_int : 1; mmr_t md_uce_int : 1; mmr_t xn_uce_int : 1; mmr_t reserved_0 : 1; mmr_t system_shutdown_int : 1; mmr_t uart_int : 1; mmr_t l1_nmi_int : 1; mmr_t stop_clock : 1; mmr_t reserved_1 : 48; } sh_local_int2_enable_s;} sh_local_int2_enable_u_t;#elsetypedef union sh_local_int2_enable_u { mmr_t sh_local_int2_enable_regval; struct { mmr_t reserved_1 : 48; mmr_t stop_clock : 1; mmr_t l1_nmi_int : 1; mmr_t uart_int : 1; mmr_t system_shutdown_int : 1; mmr_t reserved_0 : 1; mmr_t xn_uce_int : 1; mmr_t md_uce_int : 1; mmr_t pi_uce_int : 1; mmr_t xn_ce_int : 1; mmr_t md_ce_int : 1; mmr_t pi_ce_int : 1; mmr_t ii_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t md_hw_int : 1; mmr_t pi_hw_int : 1; } sh_local_int2_enable_s;} sh_local_int2_enable_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT3_CONFIG" *//* SHub Local Interrupt 3 Registers *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int3_config_u { mmr_t sh_local_int3_config_regval; struct { mmr_t type : 3; mmr_t agt : 1; mmr_t pid : 16; mmr_t reserved_0 : 1; mmr_t base : 29; mmr_t reserved_1 : 2; mmr_t idx : 8; mmr_t reserved_2 : 4; } sh_local_int3_config_s;} sh_local_int3_config_u_t;#elsetypedef union sh_local_int3_config_u { mmr_t sh_local_int3_config_regval; struct { mmr_t reserved_2 : 4; mmr_t idx : 8; mmr_t reserved_1 : 2; mmr_t base : 29; mmr_t reserved_0 : 1; mmr_t pid : 16; mmr_t agt : 1; mmr_t type : 3; } sh_local_int3_config_s;} sh_local_int3_config_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT3_ENABLE" *//* SHub Local Interrupt 3 Enable *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int3_enable_u { mmr_t sh_local_int3_enable_regval; struct { mmr_t pi_hw_int : 1; mmr_t md_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t ii_hw_int : 1; mmr_t pi_ce_int : 1; mmr_t md_ce_int : 1; mmr_t xn_ce_int : 1; mmr_t pi_uce_int : 1; mmr_t md_uce_int : 1; mmr_t xn_uce_int : 1; mmr_t reserved_0 : 1; mmr_t system_shutdown_int : 1; mmr_t uart_int : 1; mmr_t l1_nmi_int : 1; mmr_t stop_clock : 1; mmr_t reserved_1 : 48; } sh_local_int3_enable_s;} sh_local_int3_enable_u_t;#elsetypedef union sh_local_int3_enable_u { mmr_t sh_local_int3_enable_regval; struct { mmr_t reserved_1 : 48; mmr_t stop_clock : 1; mmr_t l1_nmi_int : 1; mmr_t uart_int : 1; mmr_t system_shutdown_int : 1; mmr_t reserved_0 : 1; mmr_t xn_uce_int : 1; mmr_t md_uce_int : 1; mmr_t pi_uce_int : 1; mmr_t xn_ce_int : 1; mmr_t md_ce_int : 1; mmr_t pi_ce_int : 1; mmr_t ii_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t md_hw_int : 1; mmr_t pi_hw_int : 1; } sh_local_int3_enable_s;} sh_local_int3_enable_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT4_CONFIG" *//* SHub Local Interrupt 4 Registers *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int4_config_u { mmr_t sh_local_int4_config_regval; struct { mmr_t type : 3; mmr_t agt : 1; mmr_t pid : 16; mmr_t reserved_0 : 1; mmr_t base : 29; mmr_t reserved_1 : 2; mmr_t idx : 8; mmr_t reserved_2 : 4; } sh_local_int4_config_s;} sh_local_int4_config_u_t;#elsetypedef union sh_local_int4_config_u { mmr_t sh_local_int4_config_regval; struct { mmr_t reserved_2 : 4; mmr_t idx : 8; mmr_t reserved_1 : 2; mmr_t base : 29; mmr_t reserved_0 : 1; mmr_t pid : 16; mmr_t agt : 1; mmr_t type : 3; } sh_local_int4_config_s;} sh_local_int4_config_u_t;#endif/* ==================================================================== *//* Register "SH_LOCAL_INT4_ENABLE" *//* SHub Local Interrupt 4 Enable *//* ==================================================================== */#ifdef LITTLE_ENDIANtypedef union sh_local_int4_enable_u { mmr_t sh_local_int4_enable_regval; struct { mmr_t pi_hw_int : 1; mmr_t md_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t ii_hw_int : 1; mmr_t pi_ce_int : 1; mmr_t md_ce_int : 1; mmr_t xn_ce_int : 1; mmr_t pi_uce_int : 1; mmr_t md_uce_int : 1; mmr_t xn_uce_int : 1; mmr_t reserved_0 : 1; mmr_t system_shutdown_int : 1; mmr_t uart_int : 1; mmr_t l1_nmi_int : 1; mmr_t stop_clock : 1; mmr_t reserved_1 : 48; } sh_local_int4_enable_s;} sh_local_int4_enable_u_t;#elsetypedef union sh_local_int4_enable_u { mmr_t sh_local_int4_enable_regval; struct { mmr_t reserved_1 : 48; mmr_t stop_clock : 1; mmr_t l1_nmi_int : 1; mmr_t uart_int : 1; mmr_t system_shutdown_int : 1; mmr_t reserved_0 : 1; mmr_t xn_uce_int : 1; mmr_t md_uce_int : 1; mmr_t pi_uce_int : 1; mmr_t xn_ce_int : 1; mmr_t md_ce_int : 1; mmr_t pi_ce_int : 1; mmr_t ii_hw_int : 1; mmr_t lb_hw_int : 1; mmr_t xn_hw_int : 1; mmr_t md_hw_int : 1; mmr_t pi_hw_int : 1;
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