shub_mmr_t.h

linux-2.4.29操作系统的源码

typedef union sh_gfx_stall_timer_1_u {
	mmr_t	sh_gfx_stall_timer_1_regval;
	struct {
		mmr_t	timer_value : 26;
		mmr_t	reserved_0  : 38;
	} sh_gfx_stall_timer_1_s;
} sh_gfx_stall_timer_1_u_t;
#else
typedef union sh_gfx_stall_timer_1_u {
	mmr_t	sh_gfx_stall_timer_1_regval;
	struct {
		mmr_t	reserved_0  : 38;
		mmr_t	timer_value : 26;
	} sh_gfx_stall_timer_1_s;
} sh_gfx_stall_timer_1_u_t;
#endif

/* ==================================================================== */
/*                      Register "SH_GFX_WINDOW_0"                      */
/*                   Graphics-write Window for CPU 0                    */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_gfx_window_0_u {
	mmr_t	sh_gfx_window_0_regval;
	struct {
		mmr_t	reserved_0    : 24;
		mmr_t	base_addr     : 12;
		mmr_t	reserved_1    : 27;
		mmr_t	gfx_window_en : 1;
	} sh_gfx_window_0_s;
} sh_gfx_window_0_u_t;
#else
typedef union sh_gfx_window_0_u {
	mmr_t	sh_gfx_window_0_regval;
	struct {
		mmr_t	gfx_window_en : 1;
		mmr_t	reserved_1    : 27;
		mmr_t	base_addr     : 12;
		mmr_t	reserved_0    : 24;
	} sh_gfx_window_0_s;
} sh_gfx_window_0_u_t;
#endif

/* ==================================================================== */
/*                      Register "SH_GFX_WINDOW_1"                      */
/*                   Graphics-write Window for CPU 1                    */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_gfx_window_1_u {
	mmr_t	sh_gfx_window_1_regval;
	struct {
		mmr_t	reserved_0    : 24;
		mmr_t	base_addr     : 12;
		mmr_t	reserved_1    : 27;
		mmr_t	gfx_window_en : 1;
	} sh_gfx_window_1_s;
} sh_gfx_window_1_u_t;
#else
typedef union sh_gfx_window_1_u {
	mmr_t	sh_gfx_window_1_regval;
	struct {
		mmr_t	gfx_window_en : 1;
		mmr_t	reserved_1    : 27;
		mmr_t	base_addr     : 12;
		mmr_t	reserved_0    : 24;
	} sh_gfx_window_1_s;
} sh_gfx_window_1_u_t;
#endif

/* ==================================================================== */
/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
/*               Graphics-write Interrupt Limit for CPU 0               */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_gfx_interrupt_timer_limit_0_u {
	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
	struct {
		mmr_t	interrupt_timer_limit : 8;
		mmr_t	reserved_0            : 56;
	} sh_gfx_interrupt_timer_limit_0_s;
} sh_gfx_interrupt_timer_limit_0_u_t;
#else
typedef union sh_gfx_interrupt_timer_limit_0_u {
	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
	struct {
		mmr_t	reserved_0            : 56;
		mmr_t	interrupt_timer_limit : 8;
	} sh_gfx_interrupt_timer_limit_0_s;
} sh_gfx_interrupt_timer_limit_0_u_t;
#endif

/* ==================================================================== */
/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
/*               Graphics-write Interrupt Limit for CPU 1               */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_gfx_interrupt_timer_limit_1_u {
	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
	struct {
		mmr_t	interrupt_timer_limit : 8;
		mmr_t	reserved_0            : 56;
	} sh_gfx_interrupt_timer_limit_1_s;
} sh_gfx_interrupt_timer_limit_1_u_t;
#else
typedef union sh_gfx_interrupt_timer_limit_1_u {
	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
	struct {
		mmr_t	reserved_0            : 56;
		mmr_t	interrupt_timer_limit : 8;
	} sh_gfx_interrupt_timer_limit_1_s;
} sh_gfx_interrupt_timer_limit_1_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_GFX_WRITE_STATUS_0"                   */
/*                   Graphics Write Status for CPU 0                    */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_gfx_write_status_0_u {
	mmr_t	sh_gfx_write_status_0_regval;
	struct {
		mmr_t	busy                : 1;
		mmr_t	reserved_0          : 62;
		mmr_t	re_enable_gfx_stall : 1;
	} sh_gfx_write_status_0_s;
} sh_gfx_write_status_0_u_t;
#else
typedef union sh_gfx_write_status_0_u {
	mmr_t	sh_gfx_write_status_0_regval;
	struct {
		mmr_t	re_enable_gfx_stall : 1;
		mmr_t	reserved_0          : 62;
		mmr_t	busy                : 1;
	} sh_gfx_write_status_0_s;
} sh_gfx_write_status_0_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_GFX_WRITE_STATUS_1"                   */
/*                   Graphics Write Status for CPU 1                    */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_gfx_write_status_1_u {
	mmr_t	sh_gfx_write_status_1_regval;
	struct {
		mmr_t	busy                : 1;
		mmr_t	reserved_0          : 62;
		mmr_t	re_enable_gfx_stall : 1;
	} sh_gfx_write_status_1_s;
} sh_gfx_write_status_1_u_t;
#else
typedef union sh_gfx_write_status_1_u {
	mmr_t	sh_gfx_write_status_1_regval;
	struct {
		mmr_t	re_enable_gfx_stall : 1;
		mmr_t	reserved_0          : 62;
		mmr_t	busy                : 1;
	} sh_gfx_write_status_1_s;
} sh_gfx_write_status_1_u_t;
#endif

/* ==================================================================== */
/*                        Register "SH_II_INT0"                         */
/*                    SHub II Interrupt 0 Registers                     */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ii_int0_u {
	mmr_t	sh_ii_int0_regval;
	struct {
		mmr_t	idx         : 8;
		mmr_t	send        : 1;
		mmr_t	reserved_0  : 55;
	} sh_ii_int0_s;
} sh_ii_int0_u_t;
#else
typedef union sh_ii_int0_u {
	mmr_t	sh_ii_int0_regval;
	struct {
		mmr_t	reserved_0  : 55;
		mmr_t	send        : 1;
		mmr_t	idx         : 8;
	} sh_ii_int0_s;
} sh_ii_int0_u_t;
#endif

/* ==================================================================== */
/*                     Register "SH_II_INT0_CONFIG"                     */
/*                 SHub II Interrupt 0 Config Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ii_int0_config_u {
	mmr_t	sh_ii_int0_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 14;
	} sh_ii_int0_config_s;
} sh_ii_int0_config_u_t;
#else
typedef union sh_ii_int0_config_u {
	mmr_t	sh_ii_int0_config_regval;
	struct {
		mmr_t	reserved_1  : 14;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_ii_int0_config_s;
} sh_ii_int0_config_u_t;
#endif

/* ==================================================================== */
/*                     Register "SH_II_INT0_ENABLE"                     */
/*                 SHub II Interrupt 0 Enable Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ii_int0_enable_u {
	mmr_t	sh_ii_int0_enable_regval;
	struct {
		mmr_t	ii_enable   : 1;
		mmr_t	reserved_0  : 63;
	} sh_ii_int0_enable_s;
} sh_ii_int0_enable_u_t;
#else
typedef union sh_ii_int0_enable_u {
	mmr_t	sh_ii_int0_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	ii_enable   : 1;
	} sh_ii_int0_enable_s;
} sh_ii_int0_enable_u_t;
#endif

/* ==================================================================== */
/*                        Register "SH_II_INT1"                         */
/*                    SHub II Interrupt 1 Registers                     */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ii_int1_u {
	mmr_t	sh_ii_int1_regval;
	struct {
		mmr_t	idx         : 8;
		mmr_t	send        : 1;
		mmr_t	reserved_0  : 55;
	} sh_ii_int1_s;
} sh_ii_int1_u_t;
#else
typedef union sh_ii_int1_u {
	mmr_t	sh_ii_int1_regval;
	struct {
		mmr_t	reserved_0  : 55;
		mmr_t	send        : 1;
		mmr_t	idx         : 8;
	} sh_ii_int1_s;
} sh_ii_int1_u_t;
#endif

/* ==================================================================== */
/*                     Register "SH_II_INT1_CONFIG"                     */
/*                 SHub II Interrupt 1 Config Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ii_int1_config_u {
	mmr_t	sh_ii_int1_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 14;
	} sh_ii_int1_config_s;
} sh_ii_int1_config_u_t;
#else
typedef union sh_ii_int1_config_u {
	mmr_t	sh_ii_int1_config_regval;
	struct {
		mmr_t	reserved_1  : 14;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_ii_int1_config_s;
} sh_ii_int1_config_u_t;
#endif

/* ==================================================================== */
/*                     Register "SH_II_INT1_ENABLE"                     */
/*                 SHub II Interrupt 1 Enable Registers                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ii_int1_enable_u {
	mmr_t	sh_ii_int1_enable_regval;
	struct {
		mmr_t	ii_enable   : 1;
		mmr_t	reserved_0  : 63;
	} sh_ii_int1_enable_s;
} sh_ii_int1_enable_u_t;
#else
typedef union sh_ii_int1_enable_u {
	mmr_t	sh_ii_int1_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	ii_enable   : 1;
	} sh_ii_int1_enable_s;
} sh_ii_int1_enable_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_INT_NODE_ID_CONFIG"                   */
/*                 SHub Interrupt Node ID Configuration                 */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_int_node_id_config_u {
	mmr_t	sh_int_node_id_config_regval;
	struct {
		mmr_t	node_id     : 11;
		mmr_t	id_sel      : 1;
		mmr_t	reserved_0  : 52;
	} sh_int_node_id_config_s;
} sh_int_node_id_config_u_t;
#else
typedef union sh_int_node_id_config_u {
	mmr_t	sh_int_node_id_config_regval;
	struct {
		mmr_t	reserved_0  : 52;
		mmr_t	id_sel      : 1;
		mmr_t	node_id     : 11;
	} sh_int_node_id_config_s;
} sh_int_node_id_config_u_t;
#endif

/* ==================================================================== */
/*                        Register "SH_IPI_INT"                         */
/*               SHub Inter-Processor Interrupt Registers               */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ipi_int_u {
	mmr_t	sh_ipi_int_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 2;
		mmr_t	idx         : 8;
		mmr_t	reserved_2  : 3;
		mmr_t	send        : 1;
	} sh_ipi_int_s;
} sh_ipi_int_u_t;
#else
typedef union sh_ipi_int_u {
	mmr_t	sh_ipi_int_regval;
	struct {
		mmr_t	send        : 1;
		mmr_t	reserved_2  : 3;
		mmr_t	idx         : 8;
		mmr_t	reserved_1  : 2;
		mmr_t	base        : 29;
		mmr_t	reserved_0  : 1;
		mmr_t	pid         : 16;
		mmr_t	agt         : 1;
		mmr_t	type        : 3;
	} sh_ipi_int_s;
} sh_ipi_int_u_t;
#endif

/* ==================================================================== */
/*                     Register "SH_IPI_INT_ENABLE"                     */
/*           SHub Inter-Processor Interrupt Enable Registers            */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_ipi_int_enable_u {
	mmr_t	sh_ipi_int_enable_regval;
	struct {
		mmr_t	pio_enable  : 1;
		mmr_t	reserved_0  : 63;
	} sh_ipi_int_enable_s;
} sh_ipi_int_enable_u_t;
#else
typedef union sh_ipi_int_enable_u {
	mmr_t	sh_ipi_int_enable_regval;
	struct {
		mmr_t	reserved_0  : 63;
		mmr_t	pio_enable  : 1;
	} sh_ipi_int_enable_s;
} sh_ipi_int_enable_u_t;
#endif

/* ==================================================================== */
/*                   Register "SH_LOCAL_INT0_CONFIG"                    */
/*                   SHub Local Interrupt 0 Registers                   */
/* ==================================================================== */

#ifdef LITTLE_ENDIAN
typedef union sh_local_int0_config_u {
	mmr_t	sh_local_int0_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;