ioc4.h

linux-2.4.29操作系统的源码

/* Bitmasks for IOC4_SHADOW_<3:0> */
#define IOC4_SHADOW_DR          0x00000001  /* Data ready */
#define IOC4_SHADOW_OE          0x00000002  /* Overrun error */
#define IOC4_SHADOW_PE          0x00000004  /* Parity error */
#define IOC4_SHADOW_FE          0x00000008  /* Framing error */
#define IOC4_SHADOW_BI          0x00000010  /* Break interrupt */
#define IOC4_SHADOW_THRE        0x00000020  /* Xmit holding register empty */
#define IOC4_SHADOW_TEMT        0x00000040  /* Xmit shift register empty */
#define IOC4_SHADOW_RFCE        0x00000080  /* Char in RX fifo has an error */
#define IOC4_SHADOW_DCTS        0x00010000  /* Delta clear to send */
#define IOC4_SHADOW_DDCD        0x00080000  /* Delta data carrier detect */
#define IOC4_SHADOW_CTS         0x00100000  /* Clear to send */
#define IOC4_SHADOW_DCD         0x00800000  /* Data carrier detect */
#define IOC4_SHADOW_DTR         0x01000000  /* Data terminal ready */
#define IOC4_SHADOW_RTS         0x02000000  /* Request to send */
#define IOC4_SHADOW_OUT1        0x04000000  /* 16550 OUT1 bit */
#define IOC4_SHADOW_OUT2        0x08000000  /* 16550 OUT2 bit */
#define IOC4_SHADOW_LOOP        0x10000000  /* Loopback enabled */

/* Bitmasks for IOC4_SRTR_<3:0> */
#define IOC4_SRTR_CNT	        0x00000fff /* Reload value for RX timer */
#define IOC4_SRTR_CNT_VAL	0x0fff0000 /* Current value of RX timer */
#define IOC4_SRTR_CNT_VAL_SHIFT         16
#define IOC4_SRTR_HZ                 16000 /* SRTR clock frequency */

/* Serial port register map used for DMA and PIO serial I/O */
typedef volatile struct ioc4_serialregs {
    ioc4reg_t		    sscr;
    ioc4reg_t		    stpir;
    ioc4reg_t		    stcir;
    ioc4reg_t		    srpir;
    ioc4reg_t		    srcir;
    ioc4reg_t		    srtr;
    ioc4reg_t		    shadow;
} ioc4_sregs_t;

/* IOC4 UART register map */
typedef volatile struct ioc4_uartregs {
    char                    i4u_lcr;
    union {
        char                    iir;    /* read only */
        char                    fcr;    /* write only */
    } u3;
    union {
        char                    ier;    /* DLAB == 0 */
        char                    dlm;    /* DLAB == 1 */
    } u2;
    union {
        char                    rbr;    /* read only, DLAB == 0 */
        char                    thr;    /* write only, DLAB == 0 */
        char                    dll;    /* DLAB == 1 */
    } u1;
    char                    i4u_scr;
    char                    i4u_msr;
    char                    i4u_lsr;
    char                    i4u_mcr;
} ioc4_uart_t;


#define i4u_rbr u1.rbr
#define i4u_thr u1.thr
#define i4u_dll u1.dll
#define i4u_ier u2.ier
#define i4u_dlm u2.dlm
#define i4u_iir u3.iir
#define i4u_fcr u3.fcr

/* PCI config space register map */
typedef volatile struct ioc4_configregs {
    ioc4reg_t		    pci_id;
    ioc4reg_t		    pci_scr;
    ioc4reg_t		    pci_rev;
    ioc4reg_t		    pci_lat;
    ioc4reg_t		    pci_bar0;
    ioc4reg_t		    pci_bar1;
    ioc4reg_t               pci_bar2_not_implemented;
    ioc4reg_t               pci_cis_ptr_not_implemented;
    ioc4reg_t		    pci_sidv;
    ioc4reg_t		    pci_rom_bar_not_implemented;
    ioc4reg_t		    pci_cap;
    ioc4reg_t		    pci_rsv;
    ioc4reg_t		    pci_latgntint;

    char                    pci_fill1[0x58 - 0x3c - 4];

    ioc4reg_t               pci_pcix;
    ioc4reg_t               pci_pcixstatus;
} ioc4_cfg_t;

/* PCI memory space register map addressed using pci_bar0 */
typedef volatile struct ioc4_memregs {

    /* Miscellaneous IOC4  registers */
    ioc4reg_t		    pci_err_addr_l;
    ioc4reg_t		    pci_err_addr_h;
    ioc4reg_t		    sio_ir;
    ioc4reg_t		    other_ir;

    /* These registers are read-only for general kernel code.  To
     * modify them use the functions in ioc4.c.
     */
    ioc4reg_t		    sio_ies_ro;
    ioc4reg_t		    other_ies_ro;
    ioc4reg_t		    sio_iec_ro;
    ioc4reg_t		    other_iec_ro;
    ioc4reg_t		    sio_cr;
    ioc4reg_t		    misc_fill1;
    ioc4reg_t		    int_out;
    ioc4reg_t		    misc_fill2;
    ioc4reg_t		    gpcr_s;
    ioc4reg_t		    gpcr_c;
    ioc4reg_t		    gpdr;
    ioc4reg_t		    misc_fill3;
    ioc4reg_t		    gppr_0;
    ioc4reg_t		    gppr_1;
    ioc4reg_t		    gppr_2;
    ioc4reg_t		    gppr_3;
    ioc4reg_t		    gppr_4;
    ioc4reg_t		    gppr_5;
    ioc4reg_t		    gppr_6;
    ioc4reg_t		    gppr_7;

    char		    misc_fill4[0x100 - 0x5C - 4];

    /* ATA/ATAP registers */
    ioc4reg_t		    ata_0;
    ioc4reg_t		    ata_1;
    ioc4reg_t		    ata_2;
    ioc4reg_t		    ata_3;
    ioc4reg_t		    ata_4;
    ioc4reg_t		    ata_5;
    ioc4reg_t		    ata_6;
    ioc4reg_t		    ata_7;
    ioc4reg_t		    ata_aux;

    char		    ata_fill1[0x140 - 0x120 - 4];

    ioc4reg_t		    ata_timing;
    ioc4reg_t		    ata_dma_ptr_l;
    ioc4reg_t		    ata_dma_ptr_h;
    ioc4reg_t		    ata_dma_addr_l;
    ioc4reg_t		    ata_dma_addr_h;
    ioc4reg_t		    ata_bc_dev;
    ioc4reg_t		    ata_bc_mem;
    ioc4reg_t		    ata_dma_ctrl;

    char		    ata_fill2[0x200 - 0x15C - 4];

    /* Keyboard and mouse registers */
    ioc4reg_t		    km_csr;
    ioc4reg_t		    k_rd;
    ioc4reg_t		    m_rd;
    ioc4reg_t		    k_wd;
    ioc4reg_t		    m_wd;

    char		    km_fill1[0x300 - 0x210 - 4];

    /* Serial port registers used for DMA serial I/O */
    ioc4reg_t		    sbbr01_l;
    ioc4reg_t		    sbbr01_h;
    ioc4reg_t		    sbbr23_l;
    ioc4reg_t		    sbbr23_h;

    ioc4_sregs_t	    port_0;
    ioc4_sregs_t	    port_1;
    ioc4_sregs_t	    port_2;
    ioc4_sregs_t	    port_3;

    ioc4_uart_t		    uart_0;
    ioc4_uart_t		    uart_1;
    ioc4_uart_t		    uart_2;
    ioc4_uart_t		    uart_3;
} ioc4_mem_t;


/*
 * Bytebus device space
 */
#define IOC4_BYTEBUS_DEV0	0x80000L  /* Addressed using pci_bar0 */ 
#define IOC4_BYTEBUS_DEV1	0xA0000L  /* Addressed using pci_bar0 */
#define IOC4_BYTEBUS_DEV2	0xC0000L  /* Addressed using pci_bar0 */
#define IOC4_BYTEBUS_DEV3	0xE0000L  /* Addressed using pci_bar0 */

/* UART clock speed */
#define IOC4_SER_XIN_CLK        66000000

typedef enum ioc4_subdevs_e {
    ioc4_subdev_generic,
    ioc4_subdev_kbms,
    ioc4_subdev_tty0,
    ioc4_subdev_tty1,
    ioc4_subdev_tty2,
    ioc4_subdev_tty3,
    ioc4_subdev_rt,
    ioc4_nsubdevs
} ioc4_subdev_t;

/* Subdevice disable bits,
 * from the standard INFO_LBL_SUBDEVS
 */
#define IOC4_SDB_TTY0		(1 << ioc4_subdev_tty0)
#define IOC4_SDB_TTY1		(1 << ioc4_subdev_tty1)
#define IOC4_SDB_TTY2		(1 << ioc4_subdev_tty2)
#define IOC4_SDB_TTY3		(1 << ioc4_subdev_tty3)
#define IOC4_SDB_KBMS		(1 << ioc4_subdev_kbms)
#define IOC4_SDB_RT		(1 << ioc4_subdev_rt)
#define IOC4_SDB_GENERIC	(1 << ioc4_subdev_generic)

#define IOC4_ALL_SUBDEVS	((1 << ioc4_nsubdevs) - 1)

#define IOC4_SDB_SERIAL		(IOC4_SDB_TTY0 | IOC4_SDB_TTY1 | IOC4_SDB_TTY2 | IOC4_SDB_TTY3)

#define IOC4_STD_SUBDEVS	IOC4_ALL_SUBDEVS

#define IOC4_INTA_SUBDEVS	(IOC4_SDB_SERIAL | IOC4_SDB_KBMS | IOC4_SDB_RT | IOC4_SDB_GENERIC)

extern int		ioc4_subdev_enabled(vertex_hdl_t, ioc4_subdev_t);
extern void		ioc4_subdev_enables(vertex_hdl_t, uint64_t);
extern void		ioc4_subdev_enable(vertex_hdl_t, ioc4_subdev_t);
extern void		ioc4_subdev_disable(vertex_hdl_t, ioc4_subdev_t);

/* Macros to read and write the SIO_IEC and SIO_IES registers (see the
 * comments in ioc4.c for details on why this is necessary
 */
#define IOC4_W_IES	0
#define IOC4_W_IEC	1
extern void		ioc4_write_ireg(void *, ioc4reg_t, int, ioc4_intr_type_t);

#define IOC4_WRITE_IES(ioc4, val, type)	ioc4_write_ireg(ioc4, val, IOC4_W_IES, type)
#define IOC4_WRITE_IEC(ioc4, val, type)	ioc4_write_ireg(ioc4, val, IOC4_W_IEC, type)

typedef void
ioc4_intr_func_f	(intr_arg_t, ioc4reg_t);

typedef void
ioc4_intr_connect_f	(struct pci_dev *conn_vhdl,
			 ioc4_intr_type_t,
			 ioc4reg_t,
			 ioc4_intr_func_f *,
			 intr_arg_t info,
			 vertex_hdl_t owner_vhdl,
			 vertex_hdl_t intr_dev_vhdl,
			 int (*)(intr_arg_t));

typedef void
ioc4_intr_disconnect_f	(vertex_hdl_t conn_vhdl,
			 ioc4_intr_type_t,
			 ioc4reg_t,
			 ioc4_intr_func_f *,
			 intr_arg_t info,
			 vertex_hdl_t owner_vhdl);

void ioc4_intr_connect(vertex_hdl_t, ioc4_intr_type_t, ioc4reg_t,
		  ioc4_intr_func_f *, intr_arg_t, vertex_hdl_t,
		  vertex_hdl_t);

extern int		ioc4_is_console(vertex_hdl_t conn_vhdl);

extern void		ioc4_mlreset(ioc4_cfg_t *, ioc4_mem_t *);


extern ioc4_mem_t      *ioc4_mem_ptr(void *ioc4_fastinfo);

typedef ioc4_intr_func_f *ioc4_intr_func_t;

#endif				/* _ASM_IA64_SN_IOC4_H */