ioc4.h

linux-2.4.29操作系统的源码

				 IOC4_SIO_IR_S0_RX_TIMER | \
				 IOC4_SIO_IR_S0_DELTA_DCD | \
				 IOC4_SIO_IR_S0_DELTA_CTS | \
				 IOC4_SIO_IR_S0_INT | \
				 IOC4_SIO_IR_S0_TX_EXPLICIT)
#define IOC4_SIO_IR_S1		(IOC4_SIO_IR_S1_TX_MT | \
				 IOC4_SIO_IR_S1_RX_FULL | \
				 IOC4_SIO_IR_S1_RX_HIGH | \
				 IOC4_SIO_IR_S1_RX_TIMER | \
				 IOC4_SIO_IR_S1_DELTA_DCD | \
				 IOC4_SIO_IR_S1_DELTA_CTS | \
				 IOC4_SIO_IR_S1_INT | \
				 IOC4_SIO_IR_S1_TX_EXPLICIT)
#define IOC4_SIO_IR_S2		(IOC4_SIO_IR_S2_TX_MT | \
				 IOC4_SIO_IR_S2_RX_FULL | \
				 IOC4_SIO_IR_S2_RX_HIGH | \
				 IOC4_SIO_IR_S2_RX_TIMER | \
				 IOC4_SIO_IR_S2_DELTA_DCD | \
				 IOC4_SIO_IR_S2_DELTA_CTS | \
				 IOC4_SIO_IR_S2_INT | \
				 IOC4_SIO_IR_S2_TX_EXPLICIT)
#define IOC4_SIO_IR_S3		(IOC4_SIO_IR_S3_TX_MT | \
				 IOC4_SIO_IR_S3_RX_FULL | \
				 IOC4_SIO_IR_S3_RX_HIGH | \
				 IOC4_SIO_IR_S3_RX_TIMER | \
				 IOC4_SIO_IR_S3_DELTA_DCD | \
				 IOC4_SIO_IR_S3_DELTA_CTS | \
				 IOC4_SIO_IR_S3_INT | \
				 IOC4_SIO_IR_S3_TX_EXPLICIT)

/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES  */
#define IOC4_OTHER_IR_ATA_INT           0x00000001 /* ATAPI intr pass-thru */
#define IOC4_OTHER_IR_ATA_MEMERR        0x00000002 /* ATAPI DMA PCI error */
#define IOC4_OTHER_IR_S0_MEMERR         0x00000004 /* Port 0 PCI error */
#define IOC4_OTHER_IR_S1_MEMERR         0x00000008 /* Port 1 PCI error */
#define IOC4_OTHER_IR_S2_MEMERR         0x00000010 /* Port 2 PCI error */
#define IOC4_OTHER_IR_S3_MEMERR         0x00000020 /* Port 3 PCI error */
#define IOC4_OTHER_IR_KBD_INT		0x00000040 /* Kbd/mouse intr */
#define IOC4_OTHER_IR_ATA_DMAINT        0x00000089 /* ATAPI DMA intr */
#define IOC4_OTHER_IR_RT_INT		0x00800000 /* RT output pulse */
#define IOC4_OTHER_IR_GEN_INT1		0x02000000 /* RT input pulse */
#define IOC4_OTHER_IR_GEN_INT_SHIFT	        25

/* Per device interrupt masks */
#define IOC4_OTHER_IR_ATA       (IOC4_OTHER_IR_ATA_INT | \
				 IOC4_OTHER_IR_ATA_MEMERR | \
				 IOC4_OTHER_IR_ATA_DMAINT)
#define IOC4_OTHER_IR_RT	(IOC4_OTHER_IR_RT_INT | IOC4_OTHER_IR_GEN_INT1)

/* Macro to load pending interrupts */
#define IOC4_PENDING_SIO_INTRS(mem)     (PCI_INW(&((mem)->sio_ir)) & \
				         PCI_INW(&((mem)->sio_ies_ro)))
#define IOC4_PENDING_OTHER_INTRS(mem)   (PCI_INW(&((mem)->other_ir)) & \
				         PCI_INW(&((mem)->other_ies_ro)))

/* Bitmasks for IOC4_SIO_CR */
#define IOC4_SIO_SR_CMD_PULSE		0x00000004 /* Byte bus strobe length */
#define IOC4_SIO_CR_CMD_PULSE_SHIFT              0
#define IOC4_SIO_CR_ARB_DIAG		0x00000070 /* Current non-ATA PCI bus
                                                      requester (ro) */
#define IOC4_SIO_CR_ARB_DIAG_TX0	0x00000000
#define IOC4_SIO_CR_ARB_DIAG_RX0	0x00000010
#define IOC4_SIO_CR_ARB_DIAG_TX1	0x00000020
#define IOC4_SIO_CR_ARB_DIAG_RX1	0x00000030
#define IOC4_SIO_CR_ARB_DIAG_TX2	0x00000040
#define IOC4_SIO_CR_ARB_DIAG_RX2	0x00000050
#define IOC4_SIO_CR_ARB_DIAG_TX3	0x00000060
#define IOC4_SIO_CR_ARB_DIAG_RX3	0x00000070
#define IOC4_SIO_CR_SIO_DIAG_IDLE	0x00000080 /* 0 -> active request among
                                                      serial ports (ro) */
#define IOC4_SIO_CR_ATA_DIAG_IDLE	0x00000100 /* 0 -> active request from
                                                      ATA port */
#define IOC4_SIO_CR_ATA_DIAG_ACTIVE     0x00000200 /* 1 -> ATA request is winner */ 

/* Bitmasks for IOC4_INT_OUT */
#define IOC4_INT_OUT_COUNT	        0x0000ffff /* Pulse interval timer */
#define IOC4_INT_OUT_MODE	        0x00070000 /* Mode mask */
#define IOC4_INT_OUT_MODE_0             0x00000000 /* Set output to 0 */
#define IOC4_INT_OUT_MODE_1             0x00040000 /* Set output to 1 */
#define IOC4_INT_OUT_MODE_1PULSE        0x00050000 /* Send 1 pulse */
#define IOC4_INT_OUT_MODE_PULSES        0x00060000 /* Send 1 pulse every interval */
#define IOC4_INT_OUT_MODE_SQW           0x00070000 /* Toggle output every interval */
#define IOC4_INT_OUT_DIAG	        0x40000000 /* Diag mode */
#define IOC4_INT_OUT_INT_OUT            0x80000000 /* Current state of INT_OUT */

/* Time constants for IOC4_INT_OUT */
#define IOC4_INT_OUT_NS_PER_TICK        (15 * 520) /* 15 ns PCI clock, multi=520 */
#define IOC4_INT_OUT_TICKS_PER_PULSE             3 /* Outgoing pulse lasts 3
                                                      ticks */
#define IOC4_INT_OUT_US_TO_COUNT(x)	           /* Convert uS to a count value */ \
	(((x) * 10 + IOC4_INT_OUT_NS_PER_TICK / 200) *	\
	 100 / IOC4_INT_OUT_NS_PER_TICK - 1)
#define IOC4_INT_OUT_COUNT_TO_US(x)	           /* Convert count value to uS */ \
	(((x) + 1) * IOC4_INT_OUT_NS_PER_TICK / 1000)
#define IOC4_INT_OUT_MIN_TICKS                   3 /* Min period is width of
                                                      pulse in "ticks" */
#define IOC4_INT_OUT_MAX_TICKS  IOC4_INT_OUT_COUNT /* Largest possible count */

/* Bitmasks for IOC4_GPCR */
#define IOC4_GPCR_DIR	                0x000000ff /* Tristate pin in or out */
#define IOC4_GPCR_DIR_PIN(x)              (1<<(x)) /* Access one of the DIR bits */
#define IOC4_GPCR_EDGE	                0x0000ff00 /* Extint edge or level
                                                      sensitive */
#define IOC4_GPCR_EDGE_PIN(x)        (1<<((x)+7 )) /* Access one of the EDGE bits */

/* Values for IOC4_GPCR */
#define IOC4_GPCR_INT_OUT_EN            0x00100000 /* Enable INT_OUT to pin 0 */
#define IOC4_GPCR_DIR_SER0_XCVR         0x00000010 /* Port 0 Transceiver select
                                                      enable */
#define IOC4_GPCR_DIR_SER1_XCVR         0x00000020 /* Port 1 Transceiver select
                                                      enable */
#define IOC4_GPCR_DIR_SER2_XCVR         0x00000040 /* Port 2 Transceiver select
                                                      enable */
#define IOC4_GPCR_DIR_SER3_XCVR         0x00000080 /* Port 3 Transceiver select
                                                      enable */

/* Defs for some of the generic I/O pins */
#define IOC4_GPCR_UART0_MODESEL	              0x10 /* Pin is output to port 0
                                                      mode sel */
#define IOC4_GPCR_UART1_MODESEL	              0x20 /* Pin is output to port 1
                                                      mode sel */
#define IOC4_GPCR_UART2_MODESEL	              0x40 /* Pin is output to port 2
                                                      mode sel */
#define IOC4_GPCR_UART3_MODESEL	              0x80 /* Pin is output to port 3
                                                      mode sel */

#define IOC4_GPPR_UART0_MODESEL_PIN	         4 /* GIO pin controlling
                                                      uart 0 mode select */
#define IOC4_GPPR_UART1_MODESEL_PIN	         5 /* GIO pin controlling
                                                      uart 1 mode select */
#define IOC4_GPPR_UART2_MODESEL_PIN	         6 /* GIO pin controlling
                                                      uart 2 mode select */
#define IOC4_GPPR_UART3_MODESEL_PIN	         7 /* GIO pin controlling
                                                      uart 3 mode select */

/* Bitmasks for IOC4_ATA_TIMING */
#define IOC4_ATA_TIMING_ADR_SETUP	0x00000003 /* Clocks of addr set-up */
#define IOC4_ATA_TIMING_PULSE_WIDTH	0x000001f8 /* Clocks of read or write
                                                      pulse width */
#define IOC4_ATA_TIMING_RECOVERY	0x0000fe00 /* Clocks before next read
                                                      or write */
#define IOC4_ATA_TIMING_USE_IORDY	0x00010000 /* PIO uses IORDY */

/* Bitmasks for address list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */
#define IOC4_ATA_ALE_DMA_ADDRESS        0xfffffffffffffffe

/* Bitmasks for byte count list elements pointed to by IOC4_ATA_DMA_PTR_<L|H> */
#define IOC4_ATA_BCLE_BYTE_COUNT        0x000000000000fffe
#define IOC4_ATA_BCLE_LIST_END          0x0000000080000000

/* Bitmasks for IOC4_ATA_BC_<DEV|MEM> */
#define IOC4_ATA_BC_BYTE_CNT            0x0001fffe /* Byte count */

/* Bitmasks for IOC4_ATA_DMA_CTRL */
#define IOC4_ATA_DMA_CTRL_STRAT		0x00000001 /* 1 -> start DMA engine */
#define IOC4_ATA_DMA_CTRL_STOP		0x00000002 /* 1 -> stop DMA engine */
#define IOC4_ATA_DMA_CTRL_DIR		0x00000004 /* 1 -> ATA bus data copied
                                                      to memory */
#define IOC4_ATA_DMA_CTRL_ACTIVE	0x00000008 /* DMA channel is active */
#define IOC4_ATA_DMA_CTRL_MEM_ERROR	0x00000010 /* DMA engine encountered 
						      a PCI error */
/* Bitmasks for IOC4_KM_CSR */
#define IOC4_KM_CSR_K_WRT_PEND  0x00000001 /* Kbd port xmitting or resetting */
#define IOC4_KM_CSR_M_WRT_PEND  0x00000002 /* Mouse port xmitting or resetting */
#define IOC4_KM_CSR_K_LCB       0x00000004 /* Line Cntrl Bit for last KBD write */
#define IOC4_KM_CSR_M_LCB       0x00000008 /* Same for mouse */
#define IOC4_KM_CSR_K_DATA      0x00000010 /* State of kbd data line */
#define IOC4_KM_CSR_K_CLK       0x00000020 /* State of kbd clock line */
#define IOC4_KM_CSR_K_PULL_DATA 0x00000040 /* Pull kbd data line low */
#define IOC4_KM_CSR_K_PULL_CLK  0x00000080 /* Pull kbd clock line low */
#define IOC4_KM_CSR_M_DATA      0x00000100 /* State of mouse data line */
#define IOC4_KM_CSR_M_CLK       0x00000200 /* State of mouse clock line */
#define IOC4_KM_CSR_M_PULL_DATA 0x00000400 /* Pull mouse data line low */
#define IOC4_KM_CSR_M_PULL_CLK  0x00000800 /* Pull mouse clock line low */
#define IOC4_KM_CSR_EMM_MODE	0x00001000 /* Emulation mode */
#define IOC4_KM_CSR_SIM_MODE	0x00002000 /* Clock X8 */
#define IOC4_KM_CSR_K_SM_IDLE   0x00004000 /* Keyboard is idle */
#define IOC4_KM_CSR_M_SM_IDLE   0x00008000 /* Mouse is idle */
#define IOC4_KM_CSR_K_TO	0x00010000 /* Keyboard trying to send/receive */
#define IOC4_KM_CSR_M_TO        0x00020000 /* Mouse trying to send/receive */
#define IOC4_KM_CSR_K_TO_EN     0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN =
                                              cause SIO_IR to assert */
#define IOC4_KM_CSR_M_TO_EN	0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN =
                                              cause SIO_IR to assert */
#define IOC4_KM_CSR_K_CLAMP_ONE	0x00100000 /* Pull K_CLK low after rec. one char */
#define IOC4_KM_CSR_M_CLAMP_ONE	0x00200000 /* Pull M_CLK low after rec. one char */
#define IOC4_KM_CSR_K_CLAMP_THREE \
                           	0x00400000 /* Pull K_CLK low after rec. three chars */
#define IOC4_KM_CSR_M_CLAMP_THREE \
                            	0x00800000 /* Pull M_CLK low after rec. three char */

/* Bitmasks for IOC4_K_RD and IOC4_M_RD */
#define IOC4_KM_RD_DATA_2       0x000000ff /* 3rd char recvd since last read */
#define IOC4_KM_RD_DATA_2_SHIFT          0
#define IOC4_KM_RD_DATA_1       0x0000ff00 /* 2nd char recvd since last read */
#define IOC4_KM_RD_DATA_1_SHIFT          8
#define IOC4_KM_RD_DATA_0	0x00ff0000 /* 1st char recvd since last read */
#define IOC4_KM_RD_DATA_0_SHIFT         16
#define IOC4_KM_RD_FRAME_ERR_2  0x01000000 /* Framing or parity error in byte 2 */
#define IOC4_KM_RD_FRAME_ERR_1  0x02000000 /* Same for byte 1 */
#define IOC4_KM_RD_FRAME_ERR_0  0x04000000 /* Same for byte 0 */

#define IOC4_KM_RD_KBD_MSE      0x08000000 /* 0 if from kbd, 1 if from mouse */
#define IOC4_KM_RD_OFLO	        0x10000000 /* 4th char recvd before this read */
#define IOC4_KM_RD_VALID_2      0x20000000 /* DATA_2 valid */
#define IOC4_KM_RD_VALID_1      0x40000000 /* DATA_1 valid */
#define IOC4_KM_RD_VALID_0      0x80000000 /* DATA_0 valid */
#define IOC4_KM_RD_VALID_ALL    (IOC4_KM_RD_VALID_0 | IOC4_KM_RD_VALID_1 | \
                                 IOC4_KM_RD_VALID_2)

/* Bitmasks for IOC4_K_WD & IOC4_M_WD */
#define IOC4_KM_WD_WRT_DATA     0x000000ff /* Write to keyboard/mouse port */
#define IOC4_KM_WD_WRT_DATA_SHIFT        0

/* Bitmasks for serial RX status byte */
#define IOC4_RXSB_OVERRUN       0x01       /* Char(s) lost */
#define IOC4_RXSB_PAR_ERR	0x02	   /* Parity error */
#define IOC4_RXSB_FRAME_ERR	0x04	   /* Framing error */
#define IOC4_RXSB_BREAK	        0x08	   /* Break character */
#define IOC4_RXSB_CTS	        0x10	   /* State of CTS */
#define IOC4_RXSB_DCD	        0x20	   /* State of DCD */
#define IOC4_RXSB_MODEM_VALID   0x40	   /* DCD, CTS, and OVERRUN are valid */
#define IOC4_RXSB_DATA_VALID    0x80	   /* Data byte, FRAME_ERR PAR_ERR & BREAK valid */

/* Bitmasks for serial TX control byte */
#define IOC4_TXCB_INT_WHEN_DONE 0x20       /* Interrupt after this byte is sent */
#define IOC4_TXCB_INVALID	0x00	   /* Byte is invalid */
#define IOC4_TXCB_VALID	        0x40	   /* Byte is valid */
#define IOC4_TXCB_MCR	        0x80	   /* Data<7:0> to modem control register */
#define IOC4_TXCB_DELAY	        0xc0	   /* Delay data<7:0> mSec */

/* Bitmasks for IOC4_SBBR_L */
#define IOC4_SBBR_L_SIZE	0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
#define IOC4_SBBR_L_BASE	0xfffff000 /* Lower serial ring base addr */

/* Bitmasks for IOC4_SSCR_<3:0> */
#define IOC4_SSCR_RX_THRESHOLD  0x000001ff /* Hiwater mark */
#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
#define IOC4_SSCR_HFC_EN	0x00020000 /* Hardware flow control enabled */
#define IOC4_SSCR_RX_RING_DCD   0x00040000 /* Post RX record on delta-DCD */
#define IOC4_SSCR_RX_RING_CTS   0x00080000 /* Post RX record on delta-CTS */
#define IOC4_SSCR_DIAG	        0x00200000 /* Bypass clock divider for sim */
#define IOC4_SSCR_RX_DRAIN	0x08000000 /* Drain RX buffer to memory */
#define IOC4_SSCR_DMA_EN	0x10000000 /* Enable ring buffer DMA */
#define IOC4_SSCR_DMA_PAUSE	0x20000000 /* Pause DMA */
#define IOC4_SSCR_PAUSE_STATE   0x40000000 /* Sets when PAUSE takes effect */
#define IOC4_SSCR_RESET	        0x80000000 /* Reset DMA channels */

/* All producer/comsumer pointers are the same bitfield */
#define IOC4_PROD_CONS_PTR_4K   0x00000ff8 /* For 4K buffers */
#define IOC4_PROD_CONS_PTR_1K   0x000003f8 /* For 1K buffers */
#define IOC4_PROD_CONS_PTR_OFF           3

/* Bitmasks for IOC4_STPIR_<3:0> */
/* Reserved for future register definitions */

/* Bitmasks for IOC4_STCIR_<3:0> */
#define IOC4_STCIR_BYTE_CNT     0x0f000000 /* Bytes in unpacker */
#define IOC4_STCIR_BYTE_CNT_SHIFT       24

/* Bitmasks for IOC4_SRPIR_<3:0> */
#define IOC4_SRPIR_BYTE_CNT	0x0f000000 /* Bytes in packer */
#define IOC4_SRPIR_BYTE_CNT_SHIFT       24

/* Bitmasks for IOC4_SRCIR_<3:0> */
#define IOC4_SRCIR_ARM	        0x80000000 /* Arm RX timer */