ioc4.h

linux-2.4.29操作系统的源码

/*
 * Copyright (c) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
 * 
 * This program is free software; you can redistribute it and/or modify it 
 * under the terms of version 2 of the GNU General Public License 
 * as published by the Free Software Foundation.
 * 
 * This program is distributed in the hope that it would be useful, but 
 * WITHOUT ANY WARRANTY; without even the implied warranty of 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
 * 
 * Further, this software is distributed without any warranty that it is 
 * free of the rightful claim of any third person regarding infringement 
 * or the like.  Any license provided herein, whether implied or 
 * otherwise, applies only to this software file.  Patent licenses, if 
 * any, provided herein do not apply to combinations of this program with 
 * other software, or any other product whatsoever.
 * 
 * You should have received a copy of the GNU General Public 
 * License along with this program; if not, write the Free Software 
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 * 
 * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
 * Mountain View, CA  94043, or:
 * 
 * http://www.sgi.com 
 * 
 */

#ifndef _ASM_IA64_SN_IOC4_H
#define _ASM_IA64_SN_IOC4_H


/*
 * ioc4.h - IOC4 chip header file
 */

/* Notes:
 * The IOC4 chip is a 32-bit PCI device that provides 4 serial ports,
 * an IDE bus interface, a PC keyboard/mouse interface, and a real-time
 * external interrupt interface.
 *
 * It includes an optimized DMA buffer management, and a store-and-forward
 * buffer RAM.
 *
 * All IOC4 registers are 32 bits wide.
 */
typedef uint32_t ioc4reg_t;

/*
 * PCI Configuration Space Register Address Map, use offset from IOC4 PCI
 * configuration base such that this can be used for multiple IOC4s
 */
#define IOC4_PCI_ID		0x0	/* ID */

#define IOC4_VENDOR_ID_NUM	0x10A9
#define IOC4_DEVICE_ID_NUM	0x100A 
#define IOC4_ADDRSPACE_MASK	0xfff00000ULL

#define IOC4_PCI_SCR		0x4 /* Status/Command */
#define IOC4_PCI_REV		0x8 /* Revision */
#define IOC4_PCI_LAT		0xC /* Latency Timer */
#define IOC4_PCI_BAR0		0x10 /* IOC4 base address 0 */
#define IOC4_PCI_SIDV		0x2c /* Subsys ID and vendor */
#define IOC4_PCI_CAP 		0x34 /* Capability pointer */
#define IOC4_PCI_LATGNTINT      0x3c /* Max_lat, min_gnt, int_pin, int_line */

/*
 * PCI Memory Space Map 
 */
#define IOC4_PCI_ERR_ADDR_L     0x000	/* Low Error Address */
#define IOC4_PCI_ERR_ADDR_VLD	        (0x1 << 0)
#define IOC4_PCI_ERR_ADDR_MST_ID_MSK    (0xf << 1)
#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK   (0xe << 1)
#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK   (0x1 << 1)
#define IOC4_PCI_ERR_ADDR_MUL_ERR       (0x1 << 5)
#define IOC4_PCI_ERR_ADDR_ADDR_MSK      (0x3ffffff << 6)

/* Master IDs contained in PCI_ERR_ADDR_MST_ID_MSK */
#define IOC4_MST_ID_S0_TX		0
#define IOC4_MST_ID_S0_RX		1
#define IOC4_MST_ID_S1_TX		2
#define IOC4_MST_ID_S1_RX		3
#define IOC4_MST_ID_S2_TX		4
#define IOC4_MST_ID_S2_RX		5
#define IOC4_MST_ID_S3_TX		6
#define IOC4_MST_ID_S3_RX		7
#define IOC4_MST_ID_ATA 		8

#define IOC4_PCI_ERR_ADDR_H	0x004	/* High Error Address */

#define IOC4_SIO_IR	        0x008	/* SIO Interrupt Register */
#define IOC4_OTHER_IR	        0x00C	/* Other Interrupt Register */

/* These registers are read-only for general kernel code. To modify
 * them use the functions in ioc4.c
 */
#define IOC4_SIO_IES_RO         0x010	/* SIO Interrupt Enable Set Reg */
#define IOC4_OTHER_IES_RO       0x014	/* Other Interrupt Enable Set Reg */
#define IOC4_SIO_IEC_RO         0x018	/* SIO Interrupt Enable Clear Reg */
#define IOC4_OTHER_IEC_RO       0x01C	/* Other Interrupt Enable Clear Reg */

#define IOC4_SIO_CR	        0x020	/* SIO Control Reg */
#define IOC4_INT_OUT	        0x028	/* INT_OUT Reg (realtime interrupt) */
#define IOC4_GPCR_S	        0x030	/* GenericPIO Cntrl Set Register */
#define IOC4_GPCR_C	        0x034	/* GenericPIO Cntrl Clear Register */
#define IOC4_GPDR	        0x038	/* GenericPIO Data Register */
#define IOC4_GPPR_0	        0x040	/* GenericPIO Pin Registers */
#define IOC4_GPPR_OFF	        0x4
#define IOC4_GPPR(x)	        (IOC4_GPPR_0+(x)*IOC4_GPPR_OFF)

/* ATAPI Registers */
#define IOC4_ATA_0              0x100	/* Data w/timing */
#define IOC4_ATA_1              0x104	/* Error/Features w/timing */
#define IOC4_ATA_2              0x108	/* Sector Count w/timing */
#define IOC4_ATA_3              0x10C	/* Sector Number w/timing */
#define IOC4_ATA_4              0x110   /* Cyliner Low w/timing */
#define IOC4_ATA_5              0x114	/* Cylinder High w/timing */
#define IOC4_ATA_6              0x118	/* Device/Head w/timing */
#define IOC4_ATA_7              0x11C	/* Status/Command w/timing */
#define IOC4_ATA_0_AUX          0x120	/* Aux Status/Device Cntrl w/timing */
#define IOC4_ATA_TIMING       	0x140	/* Timing value register 0 */
#define IOC4_ATA_DMA_PTR_L      0x144   /* Low Memory Pointer to DMA List */
#define IOC4_ATA_DMA_PTR_H      0x148   /* High Memory Pointer to DMA List */
#define IOC4_ATA_DMA_ADDR_L     0x14C   /* Low Memory DMA Address */
#define IOC4_ATA_DMA_ADDR_H     0x150   /* High Memory DMA Addresss */
#define IOC4_ATA_BC_DEV         0x154	/* DMA Byte Count at Device */
#define IOC4_ATA_BC_MEM         0x158	/* DMA Byte Count at Memory */
#define IOC4_ATA_DMA_CTRL       0x15C	/* DMA Control/Status */

/* Keyboard and Mouse Registers */
#define IOC4_KM_CSR	        0x200	/* Kbd and Mouse Cntrl/Status Reg */
#define IOC4_K_RD	        0x204	/* Kbd Read Data Register */
#define IOC4_M_RD	        0x208	/* Mouse Read Data Register */
#define IOC4_K_WD	        0x20C	/* Kbd Write Data Register */
#define IOC4_M_WD	        0x210	/* Mouse Write Data Register */

/* Serial Port Registers used for DMA mode serial I/O */
#define IOC4_SBBR01_H	        0x300	/* Serial Port Ring Buffers 
                                           Base Reg High for Channels 0 1*/
#define IOC4_SBBR01_L	        0x304	/* Serial Port Ring Buffers 
                                           Base Reg Low for Channels 0 1 */
#define IOC4_SBBR23_H	        0x308	/* Serial Port Ring Buffers 
                                           Base Reg High for Channels 2 3*/
#define IOC4_SBBR23_L	        0x30C	/* Serial Port Ring Buffers 
                                           Base Reg Low for Channels 2 3 */

#define IOC4_SSCR_0	        0x310	/* Serial Port 0 Control */
#define IOC4_STPIR_0	        0x314	/* Serial Port 0 TX Produce */
#define IOC4_STCIR_0	        0x318	/* Serial Port 0 TX Consume */
#define IOC4_SRPIR_0	        0x31C	/* Serial Port 0 RX Produce */
#define IOC4_SRCIR_0	        0x320	/* Serial Port 0 RX Consume */
#define IOC4_SRTR_0	        0x324	/* Serial Port 0 Receive Timer Reg */
#define IOC4_SHADOW_0		0x328	/* Serial Port 0 16550 Shadow Reg */

#define IOC4_SSCR_1	        0x32C	/* Serial Port 1 Control */
#define IOC4_STPIR_1	        0x330	/* Serial Port 1 TX Produce */
#define IOC4_STCIR_1	        0x334	/* Serial Port 1 TX Consume */
#define IOC4_SRPIR_1	        0x338   /* Serial Port 1 RX Produce */
#define IOC4_SRCIR_1	        0x33C	/* Serial Port 1 RX Consume */
#define IOC4_SRTR_1	        0x340	/* Serial Port 1 Receive Timer Reg */
#define IOC4_SHADOW_1		0x344	/* Serial Port 1 16550 Shadow Reg */

#define IOC4_SSCR_2	        0x348	/* Serial Port 2 Control */
#define IOC4_STPIR_2	        0x34C	/* Serial Port 2 TX Produce */
#define IOC4_STCIR_2	        0x350	/* Serial Port 2 TX Consume */
#define IOC4_SRPIR_2	        0x354	/* Serial Port 2 RX Produce */
#define IOC4_SRCIR_2	        0x358	/* Serial Port 2 RX Consume */
#define IOC4_SRTR_2	        0x35C	/* Serial Port 2 Receive Timer Reg */
#define IOC4_SHADOW_2		0x360	/* Serial Port 2 16550 Shadow Reg */

#define IOC4_SSCR_3	        0x364	/* Serial Port 3 Control */
#define IOC4_STPIR_3	        0x368	/* Serial Port 3 TX Produce */
#define IOC4_STCIR_3	        0x36C	/* Serial Port 3 TX Consume */
#define IOC4_SRPIR_3	        0x370	/* Serial Port 3 RX Produce */
#define IOC4_SRCIR_3	        0x374	/* Serial Port 3 RX Consume */
#define IOC4_SRTR_3	        0x378	/* Serial Port 3 Receive Timer Reg */
#define IOC4_SHADOW_3		0x37C	/* Serial Port 3 16550 Shadow Reg */

#define IOC4_UART0_BASE         0x380   /* UART 0 */
#define IOC4_UART1_BASE         0x388   /* UART 1 */
#define IOC4_UART2_BASE         0x390   /* UART 2 */
#define IOC4_UART3_BASE         0x398   /* UART 3 */

/* Private page address aliases for usermode mapping */
#define IOC4_INT_OUT_P	        0x04000	/* INT_OUT Reg */

#define IOC4_SSCR_0_P	        0x08000 /* Serial Port 0 */
#define IOC4_STPIR_0_P	        0x08004
#define IOC4_STCIR_0_P	        0x08008	/* (read-only) */
#define IOC4_SRPIR_0_P	        0x0800C	/* (read-only) */
#define IOC4_SRCIR_0_P	        0x08010
#define IOC4_SRTR_0_P	        0x08014
#define IOC4_UART_LSMSMCR_0_P   0x08018	/* (read-only) */

#define IOC4_SSCR_1_P	        0x0C000	/* Serial Port 1 */
#define IOC4_STPIR_1_P	        0x0C004
#define IOC4_STCIR_1_P	        0x0C008	/* (read-only) */
#define IOC4_SRPIR_1_P	        0x0C00C	/* (read-only) */
#define IOC4_SRCIR_1_P	        0x0C010
#define IOC4_SRTR_1_P	        0x0C014
#define IOC4_UART_LSMSMCR_1_P   0x0C018	/* (read-only) */

#define IOC4_SSCR_2_P	        0x10000	/* Serial Port 2 */
#define IOC4_STPIR_2_P	        0x10004
#define IOC4_STCIR_2_P	        0x10008	/* (read-only) */
#define IOC4_SRPIR_2_P	        0x1000C	/* (read-only) */
#define IOC4_SRCIR_2_P	        0x10010
#define IOC4_SRTR_2_P	        0x10014
#define IOC4_UART_LSMSMCR_2_P   0x10018	/* (read-only) */

#define IOC4_SSCR_3_P	        0x14000	/* Serial Port 3 */
#define IOC4_STPIR_3_P	        0x14004
#define IOC4_STCIR_3_P	        0x14008	/* (read-only) */
#define IOC4_SRPIR_3_P	        0x1400C	/* (read-only) */
#define IOC4_SRCIR_3_P	        0x14010
#define IOC4_SRTR_3_P	        0x14014
#define IOC4_UART_LSMSMCR_3_P   0x14018	/* (read-only) */

#define IOC4_ALIAS_PAGE_SIZE	0x4000

/* Interrupt types */
typedef enum ioc4_intr_type_e {
    ioc4_sio_intr_type,
    ioc4_other_intr_type,
    ioc4_num_intr_types
} ioc4_intr_type_t;
#define ioc4_first_intr_type    ioc4_sio_intr_type

/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES  */
#define IOC4_SIO_IR_S0_TX_MT		0x00000001 /* Serial port 0 TX empty */
#define IOC4_SIO_IR_S0_RX_FULL		0x00000002 /* Port 0 RX buf full */
#define IOC4_SIO_IR_S0_RX_HIGH		0x00000004 /* Port 0 RX hiwat */
#define IOC4_SIO_IR_S0_RX_TIMER		0x00000008 /* Port 0 RX timeout */
#define IOC4_SIO_IR_S0_DELTA_DCD	0x00000010 /* Port 0 delta DCD */
#define IOC4_SIO_IR_S0_DELTA_CTS	0x00000020 /* Port 0 delta CTS */
#define IOC4_SIO_IR_S0_INT	        0x00000040 /* Port 0 pass-thru intr */
#define IOC4_SIO_IR_S0_TX_EXPLICIT	0x00000080 /* Port 0 explicit TX thru */
#define IOC4_SIO_IR_S1_TX_MT		0x00000100 /* Serial port 1 */
#define IOC4_SIO_IR_S1_RX_FULL		0x00000200 /* */
#define IOC4_SIO_IR_S1_RX_HIGH		0x00000400 /* */
#define IOC4_SIO_IR_S1_RX_TIMER		0x00000800 /* */
#define IOC4_SIO_IR_S1_DELTA_DCD	0x00001000 /* */
#define IOC4_SIO_IR_S1_DELTA_CTS	0x00002000 /* */
#define IOC4_SIO_IR_S1_INT		0x00004000 /* */
#define IOC4_SIO_IR_S1_TX_EXPLICIT	0x00008000 /* */
#define IOC4_SIO_IR_S2_TX_MT		0x00010000 /* Serial port 2 */
#define IOC4_SIO_IR_S2_RX_FULL		0x00020000 /* */
#define IOC4_SIO_IR_S2_RX_HIGH		0x00040000 /* */
#define IOC4_SIO_IR_S2_RX_TIMER		0x00080000 /* */
#define IOC4_SIO_IR_S2_DELTA_DCD	0x00100000 /* */
#define IOC4_SIO_IR_S2_DELTA_CTS	0x00200000 /* */
#define IOC4_SIO_IR_S2_INT		0x00400000 /* */
#define IOC4_SIO_IR_S2_TX_EXPLICIT	0x00800000 /* */
#define IOC4_SIO_IR_S3_TX_MT		0x01000000 /* Serial port 3 */
#define IOC4_SIO_IR_S3_RX_FULL		0x02000000 /* */
#define IOC4_SIO_IR_S3_RX_HIGH		0x04000000 /* */
#define IOC4_SIO_IR_S3_RX_TIMER		0x08000000 /* */
#define IOC4_SIO_IR_S3_DELTA_DCD	0x10000000 /* */
#define IOC4_SIO_IR_S3_DELTA_CTS	0x20000000 /* */
#define IOC4_SIO_IR_S3_INT		0x40000000 /* */
#define IOC4_SIO_IR_S3_TX_EXPLICIT	0x80000000 /* */

/* Per device interrupt masks */
#define IOC4_SIO_IR_S0		(IOC4_SIO_IR_S0_TX_MT | \
				 IOC4_SIO_IR_S0_RX_FULL | \
				 IOC4_SIO_IR_S0_RX_HIGH | \