pic.h

linux-2.4.29操作系统的源码

		} pic_p_int_device_fld_s;
	} pic_p_int_device_u_t;
/*
 * Host Error Interrupt Field Register
 *
 * This register tells which bit location in the host's Interrupt Status register
 * to set or reset when any error condition happens.
 */
	typedef union pic_p_int_host_err_u {
		picreg_t	pic_p_int_host_err_regval;
		struct {
			picreg_t                :	32; /* 63:32 */
			picreg_t                :	24; /* 31:8 */
			picreg_t bridge_err_fld :	8; /* 7:0 */
		} pic_p_int_host_err_fld_s;
	} pic_p_int_host_err_u_t;
/*
 * Interrupt (x) Host Address Register
 *
 * This register allow different host address to be assigned to each interrupt
 * pin and the bit in the host.
 */
	typedef union pic_p_int_addr_u {
		picreg_t	pic_p_int_addr_regval;
		struct {
			picreg_t          :	8; /* 63:56 */
			picreg_t int_fld  :	8; /* 55:48 */
			picreg_t int_addr :	48; /* 47:0 */
		} pic_p_int_addr_fld_s;
	} pic_p_int_addr_u_t;
/*
 * Error Interrupt View Register
 *
 * This register contains the view of which interrupt occur even if they are
 * not currently enabled. The group clear is used to clear these bits just like
 * the interrupt status register bits.
 */
	typedef union pic_p_err_int_view_u {
		picreg_t	pic_p_err_int_view_regval;
		struct {
			picreg_t                  :	22; /* 63:42 */
			picreg_t int_ram_perr     :	1; /* 41:41 */
			picreg_t bus_arb_broke    :	1; /* 40:40 */
			picreg_t pci_x_req_tout   :	1; /* 39:39 */
			picreg_t pci_x_tabort     :	1; /* 38:38 */
			picreg_t pci_x_perr       :	1; /* 37:37 */
			picreg_t pci_x_serr       :	1; /* 36:36 */
			picreg_t pci_x_mretry     :	1; /* 35:35 */
			picreg_t pci_x_mtout      :	1; /* 34:34 */
			picreg_t pci_x_da_parity  :	1; /* 33:33 */
			picreg_t pci_x_ad_parity  :	1; /* 32:32 */
			picreg_t                  :	1; /* 31:31 */
			picreg_t pmu_page_fault   :	1; /* 30:30 */
			picreg_t unexpected_resp  :	1; /* 29:29 */
			picreg_t bad_xresp_packet :	1; /* 28:28 */
			picreg_t bad_xreq_packet  :	1; /* 27:27 */
			picreg_t resp_xtalk_error :	1; /* 26:26 */
			picreg_t req_xtalk_error  :	1; /* 25:25 */
			picreg_t invalid_access   :	1; /* 24:24 */
			picreg_t unsupported_xop  :	1; /* 23:23 */
			picreg_t xreq_fifo_oflow  :	1; /* 22:22 */
			picreg_t llp_rec_snerror  :	1; /* 21:21 */
			picreg_t llp_rec_cberror  :	1; /* 20:20 */
			picreg_t llp_rcty         :	1; /* 19:19 */
			picreg_t llp_tx_retry     :	1; /* 18:18 */
			picreg_t llp_tcty         :	1; /* 17:17 */
			picreg_t                  :	1; /* 16:16 */
			picreg_t pci_abort        :	1; /* 15:15 */
			picreg_t pci_parity       :	1; /* 14:14 */
			picreg_t pci_serr         :	1; /* 13:13 */
			picreg_t pci_perr         :	1; /* 12:12 */
			picreg_t pci_master_tout  :	1; /* 11:11 */
			picreg_t pci_retry_cnt    :	1; /* 10:10 */
			picreg_t xread_req_tout   :	1; /* 9:9 */
			picreg_t                  :	9; /* 8:0 */
		} pic_p_err_int_view_fld_s;
	} pic_p_err_int_view_u_t;


/*
 * Multiple Interrupt Register
 *
 * This register indicates if any interrupt occurs more than once without be-
 * ing cleared.
 */
	typedef union pic_p_mult_int_u {
		picreg_t	pic_p_mult_int_regval;
		struct {
			picreg_t                  :	22; /* 63:42 */
			picreg_t int_ram_perr     :	1; /* 41:41 */
			picreg_t bus_arb_broke    :	1; /* 40:40 */
			picreg_t pci_x_req_tout   :	1; /* 39:39 */
			picreg_t pci_x_tabort     :	1; /* 38:38 */
			picreg_t pci_x_perr       :	1; /* 37:37 */
			picreg_t pci_x_serr       :	1; /* 36:36 */
			picreg_t pci_x_mretry     :	1; /* 35:35 */
			picreg_t pci_x_mtout      :	1; /* 34:34 */
			picreg_t pci_x_da_parity  :	1; /* 33:33 */
			picreg_t pci_x_ad_parity  :	1; /* 32:32 */
			picreg_t                  :	1; /* 31:31 */
			picreg_t pmu_page_fault   :	1; /* 30:30 */
			picreg_t unexpected_resp  :	1; /* 29:29 */
			picreg_t bad_xresp_packet :	1; /* 28:28 */
			picreg_t bad_xreq_packet  :	1; /* 27:27 */
			picreg_t resp_xtalk_error :	1; /* 26:26 */
			picreg_t req_xtalk_error  :	1; /* 25:25 */
			picreg_t invalid_access   :	1; /* 24:24 */
			picreg_t unsupported_xop  :	1; /* 23:23 */
			picreg_t xreq_fifo_oflow  :	1; /* 22:22 */
			picreg_t llp_rec_snerror  :	1; /* 21:21 */
			picreg_t llp_rec_cberror  :	1; /* 20:20 */
			picreg_t llp_rcty         :	1; /* 19:19 */
			picreg_t llp_tx_retry     :	1; /* 18:18 */
			picreg_t llp_tcty         :	1; /* 17:17 */
			picreg_t                  :	1; /* 16:16 */
			picreg_t pci_abort        :	1; /* 15:15 */
			picreg_t pci_parity       :	1; /* 14:14 */
			picreg_t pci_serr         :	1; /* 13:13 */
			picreg_t pci_perr         :	1; /* 12:12 */
			picreg_t pci_master_tout  :	1; /* 11:11 */
			picreg_t pci_retry_cnt    :	1; /* 10:10 */
			picreg_t xread_req_tout   :	1; /* 9:9 */
			picreg_t                  :	1; /* 8:8 */
			picreg_t int_state        :	8; /* 7:0 */
		} pic_p_mult_int_fld_s;
	} pic_p_mult_int_u_t;
/*
 * Force Always Interrupt (x) Register
 *
 * A write to this data independent write only register will force a set inter-
 * rupt to occur as if the interrupt line had transitioned. If the interrupt line
 * is already active an addition set interrupt packet is set. All buffer flush op-
 * erations also occur on this operation.
 */


/*
 * Force Interrupt (x) Register
 *
 * A write to this data independent write only register in conjunction with
 * the assertion of the corresponding interrupt line will force a set interrupt
 * to occur as if the interrupt line had transitioned. The interrupt line must
 * be active for this operation to generate a set packet, otherwise the write
 * PIO is ignored. All buffer flush operations also occur when the set packet
 * is sent on this operation.
 */


/*
 * Device Registers
 *
 * The Device registers contain device specific and mapping information.
 */
	typedef union pic_device_reg_u {
		picreg_t	pic_device_reg_regval;
		struct {
			picreg_t               :	32; /* 63:32 */
			picreg_t               :	2; /* 31:30 */
			picreg_t en_virtual1   :	1; /* 29:29 */
			picreg_t en_error_lock :	1; /* 28:28 */
			picreg_t en_page_chk   :	1; /* 27:27 */
			picreg_t force_pci_par :	1; /* 26:26 */
			picreg_t en_virtual0   :	1; /* 25:25 */
			picreg_t               :	1; /* 24:24 */
			picreg_t dir_wrt_gen   :	1; /* 23:23 */
			picreg_t dev_size      :	1; /* 22:22 */
			picreg_t real_time     :	1; /* 21:21 */
			picreg_t               :	1; /* 20:20 */
			picreg_t swap_direct   :	1; /* 19:19 */
			picreg_t prefetch      :	1; /* 18:18 */
			picreg_t precise       :	1; /* 17:17 */
			picreg_t coherent      :	1; /* 16:16 */
			picreg_t barrier       :	1; /* 15:15 */
			picreg_t gbr           :	1; /* 14:14 */
			picreg_t dev_swap      :	1; /* 13:13 */
			picreg_t dev_io_mem    :	1; /* 12:12 */
			picreg_t dev_off       :	12; /* 11:0 */
		} pic_device_reg_fld_s;
	} pic_device_reg_u_t;
/*
 * Device (x) Write Request Buffer Flush
 *
 * When read, this register will return a 0x00 after the write buffer associat-
 * ed with the device has been flushed. (PCI Only)
 */


/*
 * Even Device Read Response Buffer Register (PCI Only)
 *
 * This register is use to allocate the read response buffers for the even num-
 * bered devices. (0,2)
 */
	typedef union pic_p_even_resp_u {
		picreg_t	pic_p_even_resp_regval;
		struct {
			picreg_t              :	32; /* 63:32 */
			picreg_t buff_14_en   :	1; /* 31:31 */
			picreg_t buff_14_vdev :	2; /* 30:29 */
			picreg_t buff_14_pdev :	1; /* 28:28 */
			picreg_t buff_12_en   :	1; /* 27:27 */
			picreg_t buff_12_vdev :	2; /* 26:25 */
			picreg_t buff_12_pdev :	1; /* 24:24 */
			picreg_t buff_10_en   :	1; /* 23:23 */
			picreg_t buff_10_vdev :	2; /* 22:21 */
			picreg_t buff_10_pdev :	1; /* 20:20 */
			picreg_t buff_8_en    :	1; /* 19:19 */
			picreg_t buff_8_vdev  :	2; /* 18:17 */
			picreg_t buff_8_pdev  :	1; /* 16:16 */
			picreg_t buff_6_en    :	1; /* 15:15 */
			picreg_t buff_6_vdev  :	2; /* 14:13 */
			picreg_t buff_6_pdev  :	1; /* 12:12 */
			picreg_t buff_4_en    :	1; /* 11:11 */
			picreg_t buff_4_vdev  :	2; /* 10:9 */
			picreg_t buff_4_pdev  :	1; /* 8:8 */
			picreg_t buff_2_en    :	1; /* 7:7 */
			picreg_t buff_2_vdev  :	2; /* 6:5 */
			picreg_t buff_2_pdev  :	1; /* 4:4 */
			picreg_t buff_0_en    :	1; /* 3:3 */
			picreg_t buff_0_vdev  :	2; /* 2:1 */
			picreg_t buff_0_pdev  :	1; /* 0:0 */
		} pic_p_even_resp_fld_s;
	} pic_p_even_resp_u_t;
/*
 * Odd Device Read Response Buffer Register (PCI Only)
 *
 * This register is use to allocate the read response buffers for the odd num-
 * bered devices. (1,3))
 */
	typedef union pic_p_odd_resp_u {
		picreg_t	pic_p_odd_resp_regval;
		struct {
			picreg_t              :	32; /* 63:32 */
			picreg_t buff_15_en   :	1; /* 31:31 */
			picreg_t buff_15_vdev :	2; /* 30:29 */
			picreg_t buff_15_pdev :	1; /* 28:28 */
			picreg_t buff_13_en   :	1; /* 27:27 */
			picreg_t buff_13_vdev :	2; /* 26:25 */
			picreg_t buff_13_pdev :	1; /* 24:24 */
			picreg_t buff_11_en   :	1; /* 23:23 */
			picreg_t buff_11_vdev :	2; /* 22:21 */
			picreg_t buff_11_pdev :	1; /* 20:20 */
			picreg_t buff_9_en    :	1; /* 19:19 */
			picreg_t buff_9_vdev  :	2; /* 18:17 */
			picreg_t buff_9_pdev  :	1; /* 16:16 */
			picreg_t buff_7_en    :	1; /* 15:15 */
			picreg_t buff_7_vdev  :	2; /* 14:13 */
			picreg_t buff_7_pdev  :	1; /* 12:12 */
			picreg_t buff_5_en    :	1; /* 11:11 */
			picreg_t buff_5_vdev  :	2; /* 10:9 */
			picreg_t buff_5_pdev  :	1; /* 8:8 */
			picreg_t buff_3_en    :	1; /* 7:7 */
			picreg_t buff_3_vdev  :	2; /* 6:5 */
			picreg_t buff_3_pdev  :	1; /* 4:4 */
			picreg_t buff_1_en    :	1; /* 3:3 */
			picreg_t buff_1_vdev  :	2; /* 2:1 */
			picreg_t buff_1_pdev  :	1; /* 0:0 */
		} pic_p_odd_resp_fld_s;
	} pic_p_odd_resp_u_t;
/*
 * Read Response Buffer Status Register (PCI Only)
 *
 * This read only register contains the current response buffer status.
 */
	typedef union pic_p_resp_status_u {
		picreg_t	pic_p_resp_status_regval;
		struct {
			picreg_t           :	32; /* 63:32 */
			picreg_t rrb_valid :	16; /* 31:16 */
			picreg_t rrb_inuse :	16; /* 15:0 */
		} pic_p_resp_status_fld_s;
	} pic_p_resp_status_u_t;
/*
 * Read Response Buffer Clear Register (PCI Only)
 *
 * A write to this register clears the current contents of the buffer.
 */
	typedef union pic_p_resp_clear_u {
		picreg_t	pic_p_resp_clear_regval;
		struct {
			picreg_t           :	32; /* 63:32 */
			picreg_t           :	16; /* 31:16 */
			picreg_t rrb_clear :	16; /* 15:0 */
		} pic_p_resp_clear_fld_s;
	} pic_p_resp_clear_u_t;
/*
 * PCI Read Response Buffer (x) Upper Address Match
 *
 * The PCI Bridge read response buffer upper address register is a read only
 * register which contains the upper 16-bits of the address and status used to
 * select the buffer for a PCI transaction.
 */
	typedef union pic_p_buf_upper_addr_match_u {
		picreg_t	pic_p_buf_upper_addr_match_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t filled   :	1; /* 31:31 */
			picreg_t armed    :	1; /* 30:30 */
			picreg_t flush    :	1; /* 29:29 */
			picreg_t xerr     :	1; /* 28:28 */
			picreg_t pkterr   :	1; /* 27:27 */
			picreg_t timeout  :	1; /* 26:26 */
			picreg_t prefetch :	1; /* 25:25 */
			picreg_t precise  :	1; /* 24:24 */
			picreg_t dw_be    :	8; /* 23:16 */
			picreg_t upp_addr :	16; /* 15:0 */
		} pic_p_buf_upper_addr_match_fld_s;
	} pic_p_buf_upper_addr_match_u_t;
/*
 * PCI Read Response Buffer (x) Lower Address Match
 *
 * The PCI Bridge read response buffer lower address Match register is a
 * read only register which contains the address and status used to select the
 * buffer for a PCI transaction.
 */
	typedef union pic_p_buf_lower_addr_match_u {
		picreg_t	pic_p_buf_lower_addr_match_regval;
		struct {
			picreg_t filled   :	1; /* 63:63 */
			picreg_t armed    :	1; /* 62:62 */
			picreg_t flush    :	1; /* 61:61 */
			picreg_t xerr     :	1; /* 60:60 */
			picreg_t pkterr   :	1; /* 59:59 */
			picreg_t timeout  :	1; /* 58:58 */
			picreg_t prefetch :	1; /* 57:57 */
			picreg_t precise  :	1; /* 56:56 */
			picreg_t dw_be    :	8; /* 55:48 */
			picreg_t upp_addr :	16; /* 47:32 */
			picreg_t low_addr :	32; /* 31:0 */
		} pic_p_buf_lower_addr_match_fld_s;
	} pic_p_buf_lower_addr_match_u_t;
/*
 * PCI Buffer (x) Flush Count with Data Touch Register
 *
 * This counter is incremented each time the corresponding response buffer
 * is flushed after at least a single data element in the buffer is used. A word
 * write to this address clears the count.
 */
	typedef union pic_flush_w_touch_u {
		picreg_t	pic_flush_w_touch_regval;
		struct {
			picreg_t           :	32; /* 63:32 */
			picreg_t           :	16; /* 31:16 */
			picreg_t touch_cnt :	16; /* 15:0 */
		} pic_flush_w_touch_fld_s;
	} pic_flush_w_touch_u_t;
/*
 * PCI Buffer (x) Flush Count w/o Data Touch Register
 *
 * This counter is incremented each time the corresponding response buffer
 * is flushed without any data element in the buffer being used. A word
 * write to this address clears the count.
 */
	typedef union pic_flush_wo_touch_u {
		picreg_t	pic_flush_wo_touch_regval;
		struct {
			picreg_t             :	32; /* 63:32 */
			picreg_t             :	16; /* 31:16 */
			picreg_t notouch_cnt :	16; /* 15:0 */
		} pic_flush_wo_touch_fld_s;
	} pic_flush_wo_touch_u_t;
/*
 * PCI Buffer (x) Request in Flight Count Register
 *
 * This counter is incremented on each bus clock while the request is in-
 * flight. A word write to this address clears the