pic.h

linux-2.4.29操作系统的源码

 * This register contains the address and device number when a page map
 * fault occurred.
 */
	typedef union pic_p_map_fault_u {
		picreg_t	pic_p_map_fault_regval;
		struct {
			picreg_t             :	32; /* 63:32 */
			picreg_t             :	10; /* 31:22 */
			picreg_t pci_addr    :	18; /* 21:4 */
			picreg_t             :	1; /* 3:3 */
			picreg_t pci_dev_num :	3; /* 2:0 */
		} pic_p_map_fault_fld_s;
	} pic_p_map_fault_u_t;
/*
 * Arbitration Register
 *
 * This register defines the priority and bus time out timing in PCI bus arbi-
 * tration.
 */
	typedef union pic_p_arb_u {
		picreg_t	pic_p_arb_regval;
		struct {
			picreg_t               :	32; /* 63:32 */
			picreg_t               :	8; /* 31:24 */
			picreg_t dev_broke     :	4; /* 23:20 */
			picreg_t               :	2; /* 19:18 */
			picreg_t req_wait_tick :	2; /* 17:16 */
			picreg_t               :	4; /* 15:12 */
			picreg_t req_wait_en   :	4; /* 11:8 */
			picreg_t disarb        :	1; /* 7:7 */
			picreg_t freeze_gnt    :	1; /* 6:6 */
			picreg_t               :	1; /* 5:5 */
			picreg_t en_bridge_hi  :	2; /* 4:3 */
			picreg_t               :	1; /* 2:2 */
			picreg_t en_bridge_lo  :	2; /* 1:0 */
		} pic_p_arb_fld_s;
	} pic_p_arb_u_t;
/*
 * Internal Ram Parity Error Register
 *
 * This register logs information about parity errors on internal ram access.
 */
	typedef union pic_p_ram_perr_u {
		picreg_t	pic_p_ram_perr_regval;
		struct {
			picreg_t         	     :	6; /* 63:58 */
			picreg_t ate_err_addr        :	10; /* 57:48 */
			picreg_t         	     :	7; /* 47:41 */
			picreg_t rd_resp_err_addr    :	9; /* 40:32 */
			picreg_t wrt_resp_err_addr   :	8; /* 31:24 */
			picreg_t         	     :	2; /* 23:22 */
			picreg_t ate_err 	     :	1; /* 21:21 */
			picreg_t rd_resp_err         :	1; /* 20:20 */
			picreg_t wrt_resp_err        :	1; /* 19:19 */
			picreg_t dbe_ate 	     :	3; /* 18:16 */
			picreg_t dbe_rd  	     :	8; /* 15:8 */
			picreg_t dbe_wrt 	     :	8; /* 7:0 */
		} pic_p_ram_perr_fld_s;
	} pic_p_ram_perr_u_t;
/*
 * Time-out Register
 *
 * This register determines retry hold off and max retries allowed for PIO
 * accesses to PCI/PCI-X.
 */
	typedef union pic_p_bus_timeout_u {
		picreg_t	pic_p_bus_timeout_regval;
		struct {
			picreg_t               :	32; /* 63:32 */
			picreg_t               :	11; /* 31:21 */
			picreg_t pci_retry_hld :	5; /* 20:16 */
			picreg_t               :	6; /* 15:10 */
			picreg_t pci_retry_cnt :	10; /* 9:0 */
		} pic_p_bus_timeout_fld_s;
	} pic_p_bus_timeout_u_t;
/*
 * PCI/PCI-X Type 1 Configuration Register
 *
 * This register is use during accesses to the PCI/PCI-X type 1 configuration
 * space. The bits in this register are used to supplement the address during
 * the configuration cycle to select the correct secondary bus and device.
 */
	typedef union pic_type1_cfg_u {
		picreg_t	pic_type1_cfg_regval;
		struct {
			picreg_t         :	32; /* 63:32 */
			picreg_t         :	8; /* 31:24 */
			picreg_t bus_num :	8; /* 23:16 */
			picreg_t dev_num :	5; /* 15:11 */
			picreg_t         :	11; /* 10:0 */
		} pic_type1_cfg_fld_s;
	} pic_type1_cfg_u_t;
/*
 * PCI Bus Error Upper Address Holding Register
 *
 * This register holds the value of the upper address on the PCI Bus when an
 * error occurs.
 */
	typedef union pic_p_pci_err_upper_u {
		picreg_t	pic_p_pci_err_upper_regval;
		struct {
			picreg_t                :	32; /* 63:32 */
			picreg_t                :	4; /* 31:28 */
			picreg_t pci_xtalk_did  :	4; /* 27:24 */
			picreg_t                :	2; /* 23:22 */
			picreg_t pci_dac        :	1; /* 21:21 */
			picreg_t pci_dev_master :	1; /* 20:20 */
			picreg_t pci_vdev       :	1; /* 19:19 */
			picreg_t pci_dev_num    :	3; /* 18:16 */
			picreg_t pci_uaddr_err  :	16; /* 15:0 */
		} pic_p_pci_err_upper_fld_s;
	} pic_p_pci_err_upper_u_t;
/*
 * PCI Bus Error Lower Address Holding Register
 *
 * This register holds the value of the lower address on the PCI Bus when an
 * error occurs.
 */
	typedef union pic_p_pci_err_lower_u {
		picreg_t	pic_p_pci_err_lower_regval;
		struct {
			picreg_t                :	4; /* 63:60 */
			picreg_t pci_xtalk_did  :	4; /* 59:56 */
			picreg_t                :	2; /* 55:54 */
			picreg_t pci_dac        :	1; /* 53:53 */
			picreg_t pci_dev_master :	1; /* 52:52 */
			picreg_t pci_vdev       :	1; /* 51:51 */
			picreg_t pci_dev_num    :	3; /* 50:48 */
			picreg_t pci_uaddr_err  :	16; /* 47:32 */
			picreg_t pci_laddr_err  :	32; /* 31:0 */
		} pic_p_pci_err_lower_fld_s;
	} pic_p_pci_err_lower_u_t;
/*
 * PCI-X Error Address Register
 *
 * This register contains the address on the PCI-X bus when an error oc-
 * curred.
 */
	typedef union pic_p_pcix_err_addr_u {
		picreg_t	pic_p_pcix_err_addr_regval;
		struct {
			picreg_t pcix_err_addr :	64; /* 63:0 */
		} pic_p_pcix_err_addr_fld_s;
	} pic_p_pcix_err_addr_u_t;
/*
 * PCI-X Error Attribute Register
 *
 * This register contains the attribute data on the PCI-X bus when an error
 * occurred.
 */
	typedef union pic_p_pcix_err_attr_u {
		picreg_t	pic_p_pcix_err_attr_regval;
		struct {
			picreg_t            :	16; /* 63:48 */
			picreg_t bus_cmd    :	4; /* 47:44 */
			picreg_t byte_cnt   :	12; /* 43:32 */
			picreg_t            :	1; /* 31:31 */
			picreg_t ns         :	1; /* 30:30 */
			picreg_t ro         :	1; /* 29:29 */
			picreg_t tag        :	5; /* 28:24 */
			picreg_t bus_num    :	8; /* 23:16 */
			picreg_t dev_num    :	5; /* 15:11 */
			picreg_t fun_num    :	3; /* 10:8 */
			picreg_t l_byte_cnt :	8; /* 7:0 */
		} pic_p_pcix_err_attr_fld_s;
	} pic_p_pcix_err_attr_u_t;
/*
 * PCI-X Error Data Register
 *
 * This register contains the Data on the PCI-X bus when an error occurred.
 */
	typedef union pic_p_pcix_err_data_u {
		picreg_t	pic_p_pcix_err_data_regval;
		struct {
			picreg_t pcix_err_data :	64; /* 63:0 */
		} pic_p_pcix_err_data_fld_s;
	} pic_p_pcix_err_data_u_t;
/*
 * PCI-X Read Request Timeout Error Register
 *
 * This register contains a pointer into the PCI-X read data structure.
 */
	typedef union pic_p_pcix_read_req_to_u {
		picreg_t	pic_p_pcix_read_req_to_regval;
		struct {
			picreg_t                :	55; /* 63:9 */
			picreg_t rd_buff_loc    :	5; /* 8:4 */
			picreg_t rd_buff_struct :	4; /* 3:0 */
		} pic_p_pcix_read_req_to_fld_s;
	} pic_p_pcix_read_req_to_u_t;
/*
 * INT_STATUS Register
 *
 * This is the current interrupt status register which maintains the current
 * status of all the interrupting devices which generated a n interrupt. This
 * register is read only and all the bits are active high. A high bit at
 * INT_STATE means the corresponding INT_N pin has been asserted
 * (low).
 */
	typedef union pic_p_int_status_u {
		picreg_t	pic_p_int_status_regval;
		struct {
			picreg_t                  :	22; /* 63:42 */
			picreg_t int_ram_perr     :	1; /* 41:41 */
			picreg_t bus_arb_broke    :	1; /* 40:40 */
			picreg_t pci_x_req_tout   :	1; /* 39:39 */
			picreg_t pci_x_tabort     :	1; /* 38:38 */
			picreg_t pci_x_perr       :	1; /* 37:37 */
			picreg_t pci_x_serr       :	1; /* 36:36 */
			picreg_t pci_x_mretry     :	1; /* 35:35 */
			picreg_t pci_x_mtout      :	1; /* 34:34 */
			picreg_t pci_x_da_parity  :	1; /* 33:33 */
			picreg_t pci_x_ad_parity  :	1; /* 32:32 */
			picreg_t                  :	1; /* 31:31 */
			picreg_t pmu_page_fault   :	1; /* 30:30 */
			picreg_t unexpected_resp  :	1; /* 29:29 */
			picreg_t bad_xresp_packet :	1; /* 28:28 */
			picreg_t bad_xreq_packet  :	1; /* 27:27 */
			picreg_t resp_xtalk_error :	1; /* 26:26 */
			picreg_t req_xtalk_error  :	1; /* 25:25 */
			picreg_t invalid_access   :	1; /* 24:24 */
			picreg_t unsupported_xop  :	1; /* 23:23 */
			picreg_t xreq_fifo_oflow  :	1; /* 22:22 */
			picreg_t llp_rec_snerror  :	1; /* 21:21 */
			picreg_t llp_rec_cberror  :	1; /* 20:20 */
			picreg_t llp_rcty         :	1; /* 19:19 */
			picreg_t llp_tx_retry     :	1; /* 18:18 */
			picreg_t llp_tcty         :	1; /* 17:17 */
			picreg_t                  :	1; /* 16:16 */
			picreg_t pci_abort        :	1; /* 15:15 */
			picreg_t pci_parity       :	1; /* 14:14 */
			picreg_t pci_serr         :	1; /* 13:13 */
			picreg_t pci_perr         :	1; /* 12:12 */
			picreg_t pci_master_tout  :	1; /* 11:11 */
			picreg_t pci_retry_cnt    :	1; /* 10:10 */
			picreg_t xread_req_tout   :	1; /* 9:9 */
			picreg_t                  :	1; /* 8:8 */
			picreg_t int_state        :	8; /* 7:0 */
		} pic_p_int_status_fld_s;
	} pic_p_int_status_u_t;
/*
 * Interrupt Enable Register
 *
 * This register enables the reporting of interrupt to the host. Each bit in this
 * register corresponds to the same bit in Interrupt Status register. All bits
 * are zero after reset.
 */
	typedef union pic_p_int_enable_u {
		picreg_t	pic_p_int_enable_regval;
		struct {
			picreg_t                     :	22; /* 63:42 */
			picreg_t en_int_ram_perr     :	1; /* 41:41 */
			picreg_t en_bus_arb_broke    :	1; /* 40:40 */
			picreg_t en_pci_x_req_tout   :	1; /* 39:39 */
			picreg_t en_pci_x_tabort     :	1; /* 38:38 */
			picreg_t en_pci_x_perr       :	1; /* 37:37 */
			picreg_t en_pci_x_serr       :	1; /* 36:36 */
			picreg_t en_pci_x_mretry     :	1; /* 35:35 */
			picreg_t en_pci_x_mtout      :	1; /* 34:34 */
			picreg_t en_pci_x_da_parity  :	1; /* 33:33 */
			picreg_t en_pci_x_ad_parity  :	1; /* 32:32 */
			picreg_t                     :	1; /* 31:31 */
			picreg_t en_pmu_page_fault   :	1; /* 30:30 */
			picreg_t en_unexpected_resp  :	1; /* 29:29 */
			picreg_t en_bad_xresp_packet :	1; /* 28:28 */
			picreg_t en_bad_xreq_packet  :	1; /* 27:27 */
			picreg_t en_resp_xtalk_error :	1; /* 26:26 */
			picreg_t en_req_xtalk_error  :	1; /* 25:25 */
			picreg_t en_invalid_access   :	1; /* 24:24 */
			picreg_t en_unsupported_xop  :	1; /* 23:23 */
			picreg_t en_xreq_fifo_oflow  :	1; /* 22:22 */
			picreg_t en_llp_rec_snerror  :	1; /* 21:21 */
			picreg_t en_llp_rec_cberror  :	1; /* 20:20 */
			picreg_t en_llp_rcty         :	1; /* 19:19 */
			picreg_t en_llp_tx_retry     :	1; /* 18:18 */
			picreg_t en_llp_tcty         :	1; /* 17:17 */
			picreg_t                     :	1; /* 16:16 */
			picreg_t en_pci_abort        :	1; /* 15:15 */
			picreg_t en_pci_parity       :	1; /* 14:14 */
			picreg_t en_pci_serr         :	1; /* 13:13 */
			picreg_t en_pci_perr         :	1; /* 12:12 */
			picreg_t en_pci_master_tout  :	1; /* 11:11 */
			picreg_t en_pci_retry_cnt    :	1; /* 10:10 */
			picreg_t en_xread_req_tout   :	1; /* 9:9 */
			picreg_t                     :	1; /* 8:8 */
			picreg_t en_int_state        :	8; /* 7:0 */
		} pic_p_int_enable_fld_s;
	} pic_p_int_enable_u_t;
/*
 * Reset Interrupt Register
 *
 * A write of a "1" clears the bit and rearms the error registers. Writes also
 * clear the error view register.
 */
	typedef union pic_p_int_rst_u {
		picreg_t	pic_p_int_rst_regval;
		struct {
			picreg_t                       :	22; /* 63:42 */
			picreg_t logv_int_ram_perr     :	1; /* 41:41 */
			picreg_t logv_bus_arb_broke    :	1; /* 40:40 */
			picreg_t logv_pci_x_req_tout   :	1; /* 39:39 */
			picreg_t logv_pci_x_tabort     :	1; /* 38:38 */
			picreg_t logv_pci_x_perr       :	1; /* 37:37 */
			picreg_t logv_pci_x_serr       :	1; /* 36:36 */
			picreg_t logv_pci_x_mretry     :	1; /* 35:35 */
			picreg_t logv_pci_x_mtout      :	1; /* 34:34 */
			picreg_t logv_pci_x_da_parity  :	1; /* 33:33 */
			picreg_t logv_pci_x_ad_parity  :	1; /* 32:32 */
			picreg_t                       :	1; /* 31:31 */
			picreg_t logv_pmu_page_fault   :	1; /* 30:30 */
			picreg_t logv_unexpected_resp  :	1; /* 29:29 */
			picreg_t logv_bad_xresp_packet :	1; /* 28:28 */
			picreg_t logv_bad_xreq_packet  :	1; /* 27:27 */
			picreg_t logv_resp_xtalk_error :	1; /* 26:26 */
			picreg_t logv_req_xtalk_error  :	1; /* 25:25 */
			picreg_t logv_invalid_access   :	1; /* 24:24 */
			picreg_t logv_unsupported_xop  :	1; /* 23:23 */
			picreg_t logv_xreq_fifo_oflow  :	1; /* 22:22 */
			picreg_t logv_llp_rec_snerror  :	1; /* 21:21 */
			picreg_t logv_llp_rec_cberror  :	1; /* 20:20 */
			picreg_t logv_llp_rcty         :	1; /* 19:19 */
			picreg_t logv_llp_tx_retry     :	1; /* 18:18 */
			picreg_t logv_llp_tcty         :	1; /* 17:17 */
			picreg_t                       :	1; /* 16:16 */
			picreg_t logv_pci_abort        :	1; /* 15:15 */
			picreg_t logv_pci_parity       :	1; /* 14:14 */
			picreg_t logv_pci_serr         :	1; /* 13:13 */
			picreg_t logv_pci_perr         :	1; /* 12:12 */
			picreg_t logv_pci_master_tout  :	1; /* 11:11 */
			picreg_t logv_pci_retry_cnt    :	1; /* 10:10 */
			picreg_t logv_xread_req_tout   :	1; /* 9:9 */
                        picreg_t                       :        2; /* 8:7 */
			picreg_t multi_clr             :	1; /* 6:6 */
			picreg_t                       :	6; /* 5:0 */
		} pic_p_int_rst_fld_s;
	} pic_p_int_rst_u_t;

/*
 * Interrupt Mode Register
 *
 * This register defines the interrupting mode of the INT_N pins.
 */
	typedef union pic_p_int_mode_u {
		picreg_t	pic_p_int_mode_regval;
		struct {
			picreg_t            :	32; /* 63:32 */
			picreg_t            :	24; /* 31:8 */
			picreg_t en_clr_pkt :	8; /* 7:0 */
		} pic_p_int_mode_fld_s;
	} pic_p_int_mode_u_t;
/*
 * Interrupt Device Select Register
 *
 * This register associates interrupt pins with devices thus allowing buffer
 * management (flushing) when a device interrupt occurs.
 */
	typedef union pic_p_int_device_u {
		picreg_t	pic_p_int_device_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t          :	8; /* 31:24 */
			picreg_t int7_dev :	3; /* 23:21 */
			picreg_t int6_dev :	3; /* 20:18 */
			picreg_t int5_dev :	3; /* 17:15 */
			picreg_t int4_dev :	3; /* 14:12 */
			picreg_t int3_dev :	3; /* 11:9 */
			picreg_t int2_dev :	3; /* 8:6 */
			picreg_t int1_dev :	3; /* 5:3 */
			picreg_t int0_dev :	3; /* 2:0 */