pic.h

linux-2.4.29操作系统的源码

#define PIC_PCIX_WRITE_BUF_2_VALID 0x00000B50

	/* PCIX Write Buffer 3 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_3_ADDR 0x00000B60

	/* PCIX Write Buffer 3 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_3_ATTRIBUTE 0x00000B68

	/* PCIX Write Buffer 3 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_3_VALID 0x00000B70

	/* PCIX Write Buffer 4 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_4_ADDR 0x00000B80

	/* PCIX Write Buffer 4 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_4_ATTRIBUTE 0x00000B88

	/* PCIX Write Buffer 4 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_4_VALID 0x00000B90

	/* PCIX Write Buffer 5 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_5_ADDR 0x00000BA0

	/* PCIX Write Buffer 5 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_5_ATTRIBUTE 0x00000BA8

	/* PCIX Write Buffer 5 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_5_VALID 0x00000BB0

	/* PCIX Write Buffer 6 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_6_ADDR 0x00000BC0

	/* PCIX Write Buffer 6 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_6_ATTRIBUTE 0x00000BC8

	/* PCIX Write Buffer 6 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_6_VALID 0x00000BD0

	/* PCIX Write Buffer 7 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_7_ADDR 0x00000BE0

	/* PCIX Write Buffer 7 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_7_ATTRIBUTE 0x00000BE8

	/* PCIX Write Buffer 7 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_7_VALID 0x00000BF0

/*********************************************************************
 * misc typedefs
 *
 */
typedef uint64_t picreg_t;

/*********************************************************************
 * PIC register structures
 *
 */

/*
 * Identification Register
 *
 * The Identification register is a read only register used by the host CPU
 * during configuration to determine the type of the widget. The format is
 * the same as defined in IEEE 1149.1 JTAG Device Identification Register.
 */
	typedef union pic_id_reg_u {
		picreg_t	pic_id_reg_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t rev_num  :	4; /* 31:28 */
			picreg_t part_num :	16; /* 27:12 */
			picreg_t mfg_num  :	11; /* 11:1 */
			picreg_t          :	1; /* 0:0 */
		} pic_id_reg_fld_s;
	} pic_id_reg_u_t;
/*
 * Status Register
 *
 * The status register is a read register which holds status information of the
 * Bus Subsection.
 */
	typedef union pic_stat_reg_u {
		picreg_t	pic_stat_reg_regval;
		struct {
			picreg_t                :	28; /* 63:36 */
			picreg_t pci_x_speed    :	2; /* 35:34 */
			picreg_t pci_x_active   :	1; /* 33:33 */
			picreg_t                :	1; /* 32:32 */
			picreg_t llp_rec_cnt    :	8; /* 31:24 */
			picreg_t llp_tx_cnt     :	8; /* 23:16 */
			picreg_t rx_credit_cnt  :	4; /* 15:12 */
			picreg_t tx_credit_cnt  :	4; /* 11:8 */
			picreg_t pci_misc_input :	8; /* 7:0 */
		} pic_stat_reg_fld_s;
	} pic_stat_reg_u_t;
/*
 * Upper Address Holding Register Bus Side Errors
 *
 * The upper address holding register is a read only register which contains
 * the upper 16-bits of the address when certain error occurs (see error cases
 * chapter). Subsequent errors are not logged until the error is cleared. The
 * last logged value is held until the group is cleared and enabled.
 */
	typedef union pic_upper_bus_err_u {
		picreg_t	pic_upper_bus_err_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t          :	16; /* 31:16 */
			picreg_t upp_addr :	16; /* 15:0 */
		} pic_upper_bus_err_fld_s;
	} pic_upper_bus_err_u_t;
/*
 * Lower Address Holding Register Bus Side Errors
 *
 * The lower address holding register is a read only register which contains
 * the address which either can be accessed as a word or double word. Sub-
 * sequent errors are not logged until the error is cleared. The last logged
 * value is held until the group is cleared and enabled.
 */
	typedef union pic_lower_bus_err_u {
		picreg_t	pic_lower_bus_err_regval;
		struct {
			picreg_t          :	16; /* 63:48 */
			picreg_t upp_addr :	16; /* 47:32 */
			picreg_t low_addr :	32; /* 31:0 */
		} pic_lower_bus_err_fld_s;
	} pic_lower_bus_err_u_t;
/*
 * Control Register
 *
 * The control register is a read/write register which holds control informa-
 * tion for the bus subsection.
 */
	typedef union pic_control_reg_u {
		picreg_t	pic_control_reg_regval;
		struct {
			picreg_t                :	32; /* 63:32 */
			picreg_t                :	4; /* 31:28 */
			picreg_t rst_pin_n      :	4; /* 27:24 */
			picreg_t                :	1; /* 23:23 */
			picreg_t mem_swap       :	1; /* 22:22 */
			picreg_t page_size      :	1; /* 21:21 */
			picreg_t                :	4; /* 20:17 */
			picreg_t f_bad_pkt      :	1; /* 16:16 */
			picreg_t llp_xbar_crd   :	4; /* 15:12 */
			picreg_t clr_rllp_cnt   :	1; /* 11:11 */
			picreg_t clr_tllp_cnt   :	1; /* 10:10 */
			picreg_t sys_end        :	1; /* 9:9 */
			picreg_t                :	3; /* 8:6 */
			picreg_t pci_speed      :	2; /* 5:4 */
			picreg_t widget_id      :	4; /* 3:0 */
		} pic_control_reg_fld_s;
	} pic_control_reg_u_t;
/*
 * PCI/PCI-X Request Time-out Value Register
 *
 * This register contains the reload value for the response timer. The request
 * timer counts every 960 nS (32 PCI clocks)
 */
	typedef union pic_pci_req_to_u {
		picreg_t	pic_pci_req_to_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t          :	12; /* 31:20 */
			picreg_t time_out :	20; /* 19:0 */
		} pic_pci_req_to_fld_s;
	} pic_pci_req_to_u_t;
/*
 * Interrupt Destination Upper Address Register
 *
 * The interrupt destination upper address register is a read/write register
 * containing the upper 16-bits of address of the host to which the interrupt
 * is targeted. In addition the target ID is also contained in this register for
 * use in Crosstalk mode.
 */
	typedef union pic_int_desc_upper_u {
		picreg_t	pic_int_desc_upper_regval;
		struct {
			picreg_t           :	32; /* 63:32 */
			picreg_t           :	12; /* 31:20 */
			picreg_t target_id :	4; /* 19:16 */
			picreg_t upp_addr  :	16; /* 15:0 */
		} pic_int_desc_upper_fld_s;
	} pic_int_desc_upper_u_t;
/*
 * Interrupt Destination Lower Address Register
 *
 * The interrupt destination lower address register is a read/write register
 * which contains the entire address of the host to which the interrupt is tar-
 * geted. In addition the target ID is also contained in this register for use in
 * Crosstalk mode.
 */
	typedef union pic_int_desc_lower_u {
		picreg_t	pic_int_desc_lower_regval;
		struct {
			picreg_t           :	12; /* 63:52 */
			picreg_t target_id :	4; /* 51:48 */
			picreg_t upp_addr  :	16; /* 47:32 */
			picreg_t low_addr  :	32; /* 31:0 */
		} pic_int_desc_lower_fld_s;
	} pic_int_desc_lower_u_t;
/*
 * Command Word Holding Register Bus Side Errors
 *
 * The command word holding is a read register that holds the command
 * word of a Crosstalk packet when errors occur on the link side (see error
 * chapter). Errors are indicated with error bits in the interrupt status regis-
 * ter. Subsequent errors are not logged until the interrupt is cleared..
 */
	typedef union pic_cmd_word_bus_err_u {
		picreg_t	pic_cmd_word_bus_err_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t didn     :	4; /* 31:28 */
			picreg_t sidn     :	4; /* 27:24 */
			picreg_t pactyp   :	4; /* 23:20 */
			picreg_t tnum     :	5; /* 19:15 */
			picreg_t coherent :	1; /* 14:14 */
			picreg_t ds       :	2; /* 13:12 */
			picreg_t gbr      :	1; /* 11:11 */
			picreg_t vbpm     :	1; /* 10:10 */
			picreg_t error    :	1; /* 9:9 */
			picreg_t barrier  :	1; /* 8:8 */
			picreg_t          :	8; /* 7:0 */
		} pic_cmd_word_bus_err_fld_s;
	} pic_cmd_word_bus_err_u_t;
/*
 * LLP Configuration Register
 *
 * This register contains the configuration information for the LLP modules
 * and is only valid on bus 0 side.
 */
	typedef union pic_llp_cfg_u {
		picreg_t	pic_llp_cfg_regval;
		struct {
			picreg_t                 :	32; /* 63:32 */
			picreg_t                 :	6; /* 31:26 */
			picreg_t llp_maxretry    :	10; /* 25:16 */
			picreg_t llp_nulltimeout :	6; /* 15:10 */
			picreg_t llp_maxburst    :	10; /* 9:0 */
		} pic_llp_cfg_fld_s;
	} pic_llp_cfg_u_t;
/*
 * PCI/PCI-X Target Flush Register
 *
 * When read, this register will return a 0x00 after all previous transfers to
 * the PCI bus subsection have completed.
 */

/*
 * Command Word Holding Register Link Side Errors
 *
 * The command word holding is a read-only register that holds the com-
 * mand word of a Crosstalk packet when request fifo overflow or unexpect-
 * ed response errors occur. Errors are indicated with error bits in the
 * interrupt status register. Subsequent errors are not logged until this inter-
 * rupt is cleared.
 */
	typedef union pic_cmd_word_link_err_u {
		picreg_t	pic_cmd_word_link_err_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t didn     :	4; /* 31:28 */
			picreg_t sidn     :	4; /* 27:24 */
			picreg_t pactyp   :	4; /* 23:20 */
			picreg_t tnum     :	5; /* 19:15 */
			picreg_t coherent :	1; /* 14:14 */
			picreg_t ds       :	2; /* 13:12 */
			picreg_t gbr      :	1; /* 11:11 */
			picreg_t vbpm     :	1; /* 10:10 */
			picreg_t error    :	1; /* 9:9 */
			picreg_t barrier  :	1; /* 8:8 */
			picreg_t          :	8; /* 7:0 */
		} pic_cmd_word_link_err_fld_s;
	} pic_cmd_word_link_err_u_t;
/*
 * PCI Response Buffer Error Upper Address Holding Reg
 *
 * The response buffer error upper address holding register is a read only
 * register which contains the upper 16-bits of the address when error asso-
 * ciated with response buffer entries occur. Subsequent errors are not
 * logged until the interrupt is cleared.
 */
	typedef union pic_pci_rbuf_err_upper_u {
		picreg_t	pic_pci_rbuf_err_upper_regval;
		struct {
			picreg_t          :	32; /* 63:32 */
			picreg_t          :	9; /* 31:23 */
			picreg_t dev_num  :	3; /* 22:20 */
			picreg_t buff_num :	4; /* 19:16 */
			picreg_t upp_addr :	16; /* 15:0 */
		} pic_pci_rbuf_err_upper_fld_s;
	} pic_pci_rbuf_err_upper_u_t;
/*
 * PCI Response Buffer Error Lower Address Holding Reg
 *
 * The response buffer error lower address holding register is a read only
 * register which contains the address of the error associated with response
 * buffer entries. Subsequent errors are not logged until the interrupt is
 * cleared.
 */
	typedef union pic_pci_rbuf_err_lower_u {
		picreg_t	pic_pci_rbuf_err_lower_regval;
		struct {
			picreg_t          :	9; /* 63:55 */
			picreg_t dev_num  :	3; /* 54:52 */
			picreg_t buff_num :	4; /* 51:48 */
			picreg_t upp_addr :	16; /* 47:32 */
			picreg_t low_addr :	32; /* 31:0 */
		} pic_pci_rbuf_err_lower_fld_s;
	} pic_pci_rbuf_err_lower_u_t;
/*
 * Test Pin Control Register
 *
 * This register selects the output function and value to the four test pins on
 * the PIC .
 */
	typedef union pic_test_pin_cntl_u {
		picreg_t	pic_test_pin_cntl_regval;
		struct {
			picreg_t            :	32; /* 63:32 */
			picreg_t            :	8; /* 31:24 */
			picreg_t tdata_out  :	8; /* 23:16 */
			picreg_t sel_tpin_7 :	2; /* 15:14 */
			picreg_t sel_tpin_6 :	2; /* 13:12 */
			picreg_t sel_tpin_5 :	2; /* 11:10 */
			picreg_t sel_tpin_4 :	2; /* 9:8 */
			picreg_t sel_tpin_3 :	2; /* 7:6 */
			picreg_t sel_tpin_2 :	2; /* 5:4 */
			picreg_t sel_tpin_1 :	2; /* 3:2 */
			picreg_t sel_tpin_0 :	2; /* 1:0 */
		} pic_test_pin_cntl_fld_s;
	} pic_test_pin_cntl_u_t;
/*
 * Address Holding Register Link Side Errors
 *
 * The address holding register is a read only register which contains the ad-
 * dress which either can be accessed as a word or double word. Subsequent
 * errors are not logged until the error is cleared. The last logged value is
 * held until the group is cleared and enabled.
 */
	typedef union pic_p_addr_lkerr_u {
		picreg_t	pic_p_addr_lkerr_regval;
		struct {
			picreg_t          :	16; /* 63:48 */
			picreg_t upp_addr :	16; /* 47:32 */
			picreg_t low_addr :	32; /* 31:0 */
		} pic_p_addr_lkerr_fld_s;
	} pic_p_addr_lkerr_u_t;
/*
 * PCI Direct Mapping Register
 *
 * This register is used to relocate a 2 GByte region for PCI to Crosstalk
 * transfers.
 */
	typedef union pic_p_dir_map_u {
		picreg_t	pic_p_dir_map_regval;
		struct {
			picreg_t            :	32; /* 63:32 */
			picreg_t            :	8; /* 31:24 */
			picreg_t dir_w_id   :	4; /* 23:20 */
			picreg_t            :	2; /* 19:18 */
			picreg_t dir_add512 :	1; /* 17:17 */
			picreg_t dir_off    :	17; /* 16:0 */
		} pic_p_dir_map_fld_s;
	} pic_p_dir_map_u_t;
/*
 * PCI Page Map Fault Address Register
 *