pic.h

linux-2.4.29操作系统的源码

#define PIC_PCI_RR_6_LOWER_ADDR_MATCH 0x00000368

	/* PCI RR 7 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_7_UPPER_ADDR_MATCH 0x00000370

	/* PCI RR 7 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_7_LOWER_ADDR_MATCH 0x00000378

	/* PCI RR 8 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_8_UPPER_ADDR_MATCH 0x00000380

	/* PCI RR 8 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_8_LOWER_ADDR_MATCH 0x00000388

	/* PCI RR 9 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_9_UPPER_ADDR_MATCH 0x00000390

	/* PCI RR 9 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_9_LOWER_ADDR_MATCH 0x00000398

	/* PCI RR 10 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_10_UPPER_ADDR_MATCH 0x000003A0

	/* PCI RR 10 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_10_LOWER_ADDR_MATCH 0x000003A8

	/* PCI RR 11 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_11_UPPER_ADDR_MATCH 0x000003B0

	/* PCI RR 11 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_11_LOWER_ADDR_MATCH 0x000003B8

	/* PCI RR 12 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_12_UPPER_ADDR_MATCH 0x000003C0

	/* PCI RR 12 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_12_LOWER_ADDR_MATCH 0x000003C8

	/* PCI RR 13 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_13_UPPER_ADDR_MATCH 0x000003D0

	/* PCI RR 13 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_13_LOWER_ADDR_MATCH 0x000003D8

	/* PCI RR 14 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_14_UPPER_ADDR_MATCH 0x000003E0

	/* PCI RR 14 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_14_LOWER_ADDR_MATCH 0x000003E8

	/* PCI RR 15 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_15_UPPER_ADDR_MATCH 0x000003F0

	/* PCI RR 15 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_15_LOWER_ADDR_MATCH 0x000003F8

	/* Buffer 0 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_0_FLUSH_CNT_WITH_DATA_TOUCH 0x00000400

	/* Buffer 0 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_0_FLUSH_CNT_W_O_DATA_TOUCH 0x00000408

	/* Buffer 0 Request in Flight Count Register  -- read/write */
#define PIC_BUF_0_REQ_IN_FLIGHT_CNT 0x00000410

	/* Buffer 0 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_0_PREFETCH_REQ_CNT 0x00000418

	/* Buffer 0 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_0_TOTAL_PCI_RETRY_CNT 0x00000420

	/* Buffer 0 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_0_MAX_PCI_RETRY_CNT 0x00000428

	/* Buffer 0 Max Latency Count Register  -- read/write */
#define PIC_BUF_0_MAX_LATENCY_CNT 0x00000430

	/* Buffer 0 Clear All Register  -- read/write */
#define PIC_BUF_0_CLEAR_ALL 0x00000438

	/* Buffer 2 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_2_FLUSH_CNT_WITH_DATA_TOUCH 0x00000440

	/* Buffer 2 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_2_FLUSH_CNT_W_O_DATA_TOUCH 0x00000448

	/* Buffer 2 Request in Flight Count Register  -- read/write */
#define PIC_BUF_2_REQ_IN_FLIGHT_CNT 0x00000450

	/* Buffer 2 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_2_PREFETCH_REQ_CNT 0x00000458

	/* Buffer 2 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_2_TOTAL_PCI_RETRY_CNT 0x00000460

	/* Buffer 2 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_2_MAX_PCI_RETRY_CNT 0x00000468

	/* Buffer 2 Max Latency Count Register  -- read/write */
#define PIC_BUF_2_MAX_LATENCY_CNT 0x00000470

	/* Buffer 2 Clear All Register  -- read/write */
#define PIC_BUF_2_CLEAR_ALL 0x00000478

	/* Buffer 4 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_4_FLUSH_CNT_WITH_DATA_TOUCH 0x00000480

	/* Buffer 4 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_4_FLUSH_CNT_W_O_DATA_TOUCH 0x00000488

	/* Buffer 4 Request in Flight Count Register  -- read/write */
#define PIC_BUF_4_REQ_IN_FLIGHT_CNT 0x00000490

	/* Buffer 4 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_4_PREFETCH_REQ_CNT 0x00000498

	/* Buffer 4 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_4_TOTAL_PCI_RETRY_CNT 0x000004A0

	/* Buffer 4 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_4_MAX_PCI_RETRY_CNT 0x000004A8

	/* Buffer 4 Max Latency Count Register  -- read/write */
#define PIC_BUF_4_MAX_LATENCY_CNT 0x000004B0

	/* Buffer 4 Clear All Register  -- read/write */
#define PIC_BUF_4_CLEAR_ALL 0x000004B8

	/* Buffer 6 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_6_FLUSH_CNT_WITH_DATA_TOUCH 0x000004C0

	/* Buffer 6 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_6_FLUSH_CNT_W_O_DATA_TOUCH 0x000004C8

	/* Buffer 6 Request in Flight Count Register  -- read/write */
#define PIC_BUF_6_REQ_IN_FLIGHT_CNT 0x000004D0

	/* Buffer 6 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_6_PREFETCH_REQ_CNT 0x000004D8

	/* Buffer 6 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_6_TOTAL_PCI_RETRY_CNT 0x000004E0

	/* Buffer 6 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_6_MAX_PCI_RETRY_CNT 0x000004E8

	/* Buffer 6 Max Latency Count Register  -- read/write */
#define PIC_BUF_6_MAX_LATENCY_CNT 0x000004F0

	/* Buffer 6 Clear All Register  -- read/write */
#define PIC_BUF_6_CLEAR_ALL 0x000004F8

	/* Buffer 8 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_8_FLUSH_CNT_WITH_DATA_TOUCH 0x00000500

	/* Buffer 8 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_8_FLUSH_CNT_W_O_DATA_TOUCH 0x00000508

	/* Buffer 8 Request in Flight Count Register  -- read/write */
#define PIC_BUF_8_REQ_IN_FLIGHT_CNT 0x00000510

	/* Buffer 8 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_8_PREFETCH_REQ_CNT 0x00000518

	/* Buffer 8 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_8_TOTAL_PCI_RETRY_CNT 0x00000520

	/* Buffer 8 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_8_MAX_PCI_RETRY_CNT 0x00000528

	/* Buffer 8 Max Latency Count Register  -- read/write */
#define PIC_BUF_8_MAX_LATENCY_CNT 0x00000530

	/* Buffer 8 Clear All Register  -- read/write */
#define PIC_BUF_8_CLEAR_ALL 0x00000538

	/* Buffer 10 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_10_FLUSH_CNT_WITH_DATA_TOUCH 0x00000540

	/* Buffer 10 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_10_FLUSH_CNT_W_O_DATA_TOUCH 0x00000548

	/* Buffer 10 Request in Flight Count Register  -- read/write */
#define PIC_BUF_10_REQ_IN_FLIGHT_CNT 0x00000550

	/* Buffer 10 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_10_PREFETCH_REQ_CNT 0x00000558

	/* Buffer 10 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_10_TOTAL_PCI_RETRY_CNT 0x00000560

	/* Buffer 10 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_10_MAX_PCI_RETRY_CNT 0x00000568

	/* Buffer 10 Max Latency Count Register  -- read/write */
#define PIC_BUF_10_MAX_LATENCY_CNT 0x00000570

	/* Buffer 10 Clear All Register  -- read/write */
#define PIC_BUF_10_CLEAR_ALL 0x00000578

	/* Buffer 12 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_12_FLUSH_CNT_WITH_DATA_TOUCH 0x00000580

	/* Buffer 12 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_12_FLUSH_CNT_W_O_DATA_TOUCH 0x00000588

	/* Buffer 12 Request in Flight Count Register  -- read/write */
#define PIC_BUF_12_REQ_IN_FLIGHT_CNT 0x00000590

	/* Buffer 12 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_12_PREFETCH_REQ_CNT 0x00000598

	/* Buffer 12 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_12_TOTAL_PCI_RETRY_CNT 0x000005A0

	/* Buffer 12 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_12_MAX_PCI_RETRY_CNT 0x000005A8

	/* Buffer 12 Max Latency Count Register  -- read/write */
#define PIC_BUF_12_MAX_LATENCY_CNT 0x000005B0

	/* Buffer 12 Clear All Register  -- read/write */
#define PIC_BUF_12_CLEAR_ALL 0x000005B8

	/* Buffer 14 Flush Count with Data Touch Register  -- read/write */
#define PIC_BUF_14_FLUSH_CNT_WITH_DATA_TOUCH 0x000005C0

	/* Buffer 14 Flush Count w/o Data Touch Register  -- read/write */
#define PIC_BUF_14_FLUSH_CNT_W_O_DATA_TOUCH 0x000005C8

	/* Buffer 14 Request in Flight Count Register  -- read/write */
#define PIC_BUF_14_REQ_IN_FLIGHT_CNT 0x000005D0

	/* Buffer 14 Prefetch Request Count Register  -- read/write */
#define PIC_BUF_14_PREFETCH_REQ_CNT 0x000005D8

	/* Buffer 14 Total PCI Retry Count Register  -- read/write */
#define PIC_BUF_14_TOTAL_PCI_RETRY_CNT 0x000005E0

	/* Buffer 14 Max PCI Retry Count Register  -- read/write */
#define PIC_BUF_14_MAX_PCI_RETRY_CNT 0x000005E8

	/* Buffer 14 Max Latency Count Register  -- read/write */
#define PIC_BUF_14_MAX_LATENCY_CNT 0x000005F0

	/* Buffer 14 Clear All Register  -- read/write */
#define PIC_BUF_14_CLEAR_ALL 0x000005F8

	/* PCIX Read Buffer 0 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_0_ADDR 0x00000A00

	/* PCIX Read Buffer 0 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_0_ATTRIBUTE 0x00000A08

	/* PCIX Read Buffer 1 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_1_ADDR 0x00000A10

	/* PCIX Read Buffer 1 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_1_ATTRIBUTE 0x00000A18

	/* PCIX Read Buffer 2 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_2_ADDR 0x00000A20

	/* PCIX Read Buffer 2 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_2_ATTRIBUTE 0x00000A28

	/* PCIX Read Buffer 3 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_3_ADDR 0x00000A30

	/* PCIX Read Buffer 3 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_3_ATTRIBUTE 0x00000A38

	/* PCIX Read Buffer 4 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_4_ADDR 0x00000A40

	/* PCIX Read Buffer 4 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_4_ATTRIBUTE 0x00000A48

	/* PCIX Read Buffer 5 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_5_ADDR 0x00000A50

	/* PCIX Read Buffer 5 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_5_ATTRIBUTE 0x00000A58

	/* PCIX Read Buffer 6 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_6_ADDR 0x00000A60

	/* PCIX Read Buffer 6 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_6_ATTRIBUTE 0x00000A68

	/* PCIX Read Buffer 7 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_7_ADDR 0x00000A70

	/* PCIX Read Buffer 7 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_7_ATTRIBUTE 0x00000A78

	/* PCIX Read Buffer 8 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_8_ADDR 0x00000A80

	/* PCIX Read Buffer 8 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_8_ATTRIBUTE 0x00000A88

	/* PCIX Read Buffer 9 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_9_ADDR 0x00000A90

	/* PCIX Read Buffer 9 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_9_ATTRIBUTE 0x00000A98

	/* PCIX Read Buffer 10 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_10_ADDR 0x00000AA0

	/* PCIX Read Buffer 10 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_10_ATTRIBUTE 0x00000AA8

	/* PCIX Read Buffer 11 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_11_ADDR 0x00000AB0

	/* PCIX Read Buffer 11 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_11_ATTRIBUTE 0x00000AB8

	/* PCIX Read Buffer 12 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_12_ADDR 0x00000AC0

	/* PCIX Read Buffer 12 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_12_ATTRIBUTE 0x00000AC8

	/* PCIX Read Buffer 13 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_13_ADDR 0x00000AD0

	/* PCIX Read Buffer 13 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_13_ATTRIBUTE 0x00000AD8

	/* PCIX Read Buffer 14 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_14_ADDR 0x00000AE0

	/* PCIX Read Buffer 14 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_14_ATTRIBUTE 0x00000AE8

	/* PCIX Read Buffer 15 Address Register  -- read-only */
#define PIC_PCIX_READ_BUF_15_ADDR 0x00000AF0

	/* PCIX Read Buffer 15 Attribute Register  -- read-only */
#define PIC_PCIX_READ_BUF_15_ATTRIBUTE 0x00000AF8

	/* PCIX Write Buffer 0 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_0_ADDR 0x00000B00

	/* PCIX Write Buffer 0 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_0_ATTRIBUTE 0x00000B08

	/* PCIX Write Buffer 0 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_0_VALID 0x00000B10

	/* PCIX Write Buffer 1 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_1_ADDR 0x00000B20

	/* PCIX Write Buffer 1 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_1_ATTRIBUTE 0x00000B28

	/* PCIX Write Buffer 1 Valid Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_1_VALID 0x00000B30

	/* PCIX Write Buffer 2 Address Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_2_ADDR 0x00000B40

	/* PCIX Write Buffer 2 Attribute Register  -- read-only */
#define PIC_PCIX_WRITE_BUF_2_ATTRIBUTE 0x00000B48

	/* PCIX Write Buffer 2 Valid Register  -- read-only */