pic.h

linux-2.4.29操作系统的源码

/* $Id$
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
 */
#ifndef _ASM_SN_PCI_PIC_H
#define _ASM_SN_PCI_PIC_H


/*
 * The PIC ASIC is a follow-on to the Bridge and Xbridge ASICs.
 * It shares many of the same registers as those chips and therefore
 * the primary structure for the PIC will be bridge_s as defined
 * in irix/kern/sys/PCI/bridge.h.   This file is intended as a complement
 * to bridge.h, which includes this file.  
 */

/*
 * PIC AS DEVICE ZERO
 * ------------------
 *
 * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
 * be designated as 'device 0'.   That is a departure from earlier SGI
 * PCI bridges.  Because of that we use config space 1 to access the
 * config space of the first actual PCI device on the bus. 
 * Here's what the PIC manual says:
 *
 *     The current PCI-X bus specification now defines that the parent
 *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
 *     reduced the total number of devices from 8 to 4 and removed the
 *     device registers and windows, now only supporting devices 0,1,2, and
 *     3. PIC did leave all 8 configuration space windows. The reason was
 *     there was nothing to gain by removing them. Here in lies the problem.
 *     The device numbering we do using 0 through 3 is unrelated to the device
 *     numbering which PCI-X requires in configuration space. In the past we
 *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
 *     PCI-X requires we start a 1, not 0 and currently the PX brick
 *     does associate our:
 * 
 *         device 0 with configuration space window 1,
 *         device 1 with configuration space window 2, 
 *         device 2 with configuration space window 3,
 *         device 3 with configuration space window 4.
 *
 * The net effect is that all config space access are off-by-one with 
 * relation to other per-slot accesses on the PIC.   
 * Here is a table that shows some of that:
 *
 *                               Internal Slot#
 *           |
 *           |     0         1        2         3
 * ----------|---------------------------------------
 * config    |  0x21000   0x22000  0x23000   0x24000
 *           |
 * even rrb  |  0[0]      n/a      1[0]      n/a	[] == implied even/odd
 *           |
 * odd rrb   |  n/a       0[1]     n/a       1[1]
 *           |
 * int dev   |  00       01        10        11
 *           |
 * ext slot# |  1        2         3         4
 * ----------|---------------------------------------
 */


#ifndef __ASSEMBLY__

#ifdef __cplusplus
extern "C" {
#endif


/*********************************************************************
 *    bus provider function table
 *
 *	Normally, this table is only handed off explicitly
 *	during provider initialization, and the PCI generic
 *	layer will stash a pointer to it in the vertex; however,
 *	exporting it explicitly enables a performance hack in
 *	the generic PCI provider where if we know at compile
 *	time that the only possible PCI provider is a
 *	pcibr, we can go directly to this ops table.
 */

#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/sn/pci/pciio.h>
extern pciio_provider_t pci_pic_provider;
#else
#include <linux/config.h>
#endif


/*********************************************************************
 * misc defines
 *
 */
#define PIC_WIDGET_PART_NUM_BUS0 0xd102
#define PIC_WIDGET_PART_NUM_BUS1 0xd112
#define PIC_WIDGET_MFGR_NUM 0x24
#define PIC_WIDGET_REV_A  0x1

#define IS_PIC_PART_REV_A(rev) \
	((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_A)) || \
	(rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_A)))

/*********************************************************************
 * register offset defines
 *
 */
	/* Identification Register  -- read-only */
#define PIC_IDENTIFICATION 0x00000000

	/* Status Register  -- read-only */
#define PIC_STATUS 0x00000008

	/* Upper Address Holding Register Bus Side Errors  -- read-only */
#define PIC_UPPER_ADDR_REG_BUS_SIDE_ERRS 0x00000010

	/* Lower Address Holding Register Bus Side Errors  -- read-only */
#define PIC_LOWER_ADDR_REG_BUS_SIDE_ERRS 0x00000018

	/* Control Register  -- read/write */
#define PIC_CONTROL 0x00000020

	/* PCI Request Time-out Value Register  -- read/write */
#define PIC_PCI_REQ_TIME_OUT_VALUE 0x00000028

	/* Interrupt Destination Upper Address Register  -- read/write */
#define PIC_INTR_DEST_UPPER_ADDR 0x00000030

	/* Interrupt Destination Lower Address Register  -- read/write */
#define PIC_INTR_DEST_LOWER_ADDR 0x00000038

	/* Command Word Holding Register Bus Side  -- read-only */
#define PIC_CMD_WORD_REG_BUS_SIDE 0x00000040

	/* LLP Configuration Register (Bus 0 Only)  -- read/write */
#define PIC_LLP_CFG_REG_(BUS_0_ONLY) 0x00000048

	/* PCI Target Flush Register  -- read-only */
#define PIC_PCI_TARGET_FLUSH 0x00000050

	/* Command Word Holding Register Link Side  -- read-only */
#define PIC_CMD_WORD_REG_LINK_SIDE 0x00000058

	/* Response Buffer Error Upper Address Holding  -- read-only */
#define PIC_RESP_BUF_ERR_UPPER_ADDR_ 0x00000060

	/* Response Buffer Error Lower Address Holding  -- read-only */
#define PIC_RESP_BUF_ERR_LOWER_ADDR_ 0x00000068

	/* Test Pin Control Register  -- read/write */
#define PIC_TEST_PIN_CONTROL 0x00000070

	/* Address Holding Register Link Side Errors  -- read-only */
#define PIC_ADDR_REG_LINK_SIDE_ERRS 0x00000078

	/* Direct Map Register  -- read/write */
#define PIC_DIRECT_MAP 0x00000080

	/* PCI Map Fault Address Register  -- read-only */
#define PIC_PCI_MAP_FAULT_ADDR 0x00000090

	/* Arbitration Priority Register  -- read/write */
#define PIC_ARBITRATION_PRIORITY 0x000000A0

	/* Internal Ram Parity Error Register  -- read-only */
#define PIC_INTERNAL_RAM_PARITY_ERR 0x000000B0

	/* PCI Time-out Register  -- read/write */
#define PIC_PCI_TIME_OUT 0x000000C0

	/* PCI Type 1 Configuration Register  -- read/write */
#define PIC_PCI_TYPE_1_CFG 0x000000C8

	/* PCI Bus Error Upper Address Holding Register  -- read-only */
#define PIC_PCI_BUS_ERR_UPPER_ADDR_ 0x000000D0

	/* PCI Bus Error Lower Address Holding Register  -- read-only */
#define PIC_PCI_BUS_ERR_LOWER_ADDR_ 0x000000D8

	/* PCIX Error Address Register  -- read-only */
#define PIC_PCIX_ERR_ADDR 0x000000E0

	/* PCIX Error Attribute Register  -- read-only */
#define PIC_PCIX_ERR_ATTRIBUTE 0x000000E8

	/* PCIX Error Data Register  -- read-only */
#define PIC_PCIX_ERR_DATA 0x000000F0

	/* PCIX Read Request Timeout Error Register  -- read-only */
#define PIC_PCIX_READ_REQ_TIMEOUT_ERR 0x000000F8

	/* Interrupt Status Register  -- read-only */
#define PIC_INTR_STATUS 0x00000100

	/* Interrupt Enable Register  -- read/write */
#define PIC_INTR_ENABLE 0x00000108

	/* Reset Interrupt Status Register  -- write-only */
#define PIC_RESET_INTR_STATUS 0x00000110

	/* Interrupt Mode Register  -- read/write */
#define PIC_INTR_MODE 0x00000118

	/* Interrupt Device Register  -- read/write */
#define PIC_INTR_DEVICE 0x00000120

	/* Host Error Field Register  -- read/write */
#define PIC_HOST_ERR_FIELD 0x00000128

	/* Interrupt Pin 0 Host Address Register  -- read/write */
#define PIC_INTR_PIN_0_HOST_ADDR 0x00000130

	/* Interrupt Pin 1 Host Address Register  -- read/write */
#define PIC_INTR_PIN_1_HOST_ADDR 0x00000138

	/* Interrupt Pin 2 Host Address Register  -- read/write */
#define PIC_INTR_PIN_2_HOST_ADDR 0x00000140

	/* Interrupt Pin 3 Host Address Register  -- read/write */
#define PIC_INTR_PIN_3_HOST_ADDR 0x00000148

	/* Interrupt Pin 4 Host Address Register  -- read/write */
#define PIC_INTR_PIN_4_HOST_ADDR 0x00000150

	/* Interrupt Pin 5 Host Address Register  -- read/write */
#define PIC_INTR_PIN_5_HOST_ADDR 0x00000158

	/* Interrupt Pin 6 Host Address Register  -- read/write */
#define PIC_INTR_PIN_6_HOST_ADDR 0x00000160

	/* Interrupt Pin 7 Host Address Register  -- read/write */
#define PIC_INTR_PIN_7_HOST_ADDR 0x00000168

	/* Error Interrupt View Register  -- read-only */
#define PIC_ERR_INTR_VIEW 0x00000170

	/* Multiple Interrupt Register  -- read-only */
#define PIC_MULTIPLE_INTR 0x00000178

	/* Force Always Interrupt 0 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_0 0x00000180

	/* Force Always Interrupt 1 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_1 0x00000188

	/* Force Always Interrupt 2 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_2 0x00000190

	/* Force Always Interrupt 3 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_3 0x00000198

	/* Force Always Interrupt 4 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_4 0x000001A0

	/* Force Always Interrupt 5 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_5 0x000001A8

	/* Force Always Interrupt 6 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_6 0x000001B0

	/* Force Always Interrupt 7 Register  -- write-only */
#define PIC_FORCE_ALWAYS_INTR_7 0x000001B8

	/* Force w/Pin Interrupt 0 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_0 0x000001C0

	/* Force w/Pin Interrupt 1 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_1 0x000001C8

	/* Force w/Pin Interrupt 2 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_2 0x000001D0

	/* Force w/Pin Interrupt 3 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_3 0x000001D8

	/* Force w/Pin Interrupt 4 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_4 0x000001E0

	/* Force w/Pin Interrupt 5 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_5 0x000001E8

	/* Force w/Pin Interrupt 6 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_6 0x000001F0

	/* Force w/Pin Interrupt 7 Register  -- write-only */
#define PIC_FORCE_PIN_INTR_7 0x000001F8

	/* Device 0 Register  -- read/write */
#define PIC_DEVICE_0 0x00000200

	/* Device 1 Register  -- read/write */
#define PIC_DEVICE_1 0x00000208

	/* Device 2 Register  -- read/write */
#define PIC_DEVICE_2 0x00000210

	/* Device 3 Register  -- read/write */
#define PIC_DEVICE_3 0x00000218

	/* Device 0 Write Request Buffer Register  -- read-only */
#define PIC_DEVICE_0_WRITE_REQ_BUF 0x00000240

	/* Device 1 Write Request Buffer Register  -- read-only */
#define PIC_DEVICE_1_WRITE_REQ_BUF 0x00000248

	/* Device 2 Write Request Buffer Register  -- read-only */
#define PIC_DEVICE_2_WRITE_REQ_BUF 0x00000250

	/* Device 3 Write Request Buffer Register  -- read-only */
#define PIC_DEVICE_3_WRITE_REQ_BUF 0x00000258

	/* Even Device Response Buffer Register  -- read/write */
#define PIC_EVEN_DEVICE_RESP_BUF 0x00000280

	/* Odd Device Response Buffer Register  -- read/write */
#define PIC_ODD_DEVICE_RESP_BUF 0x00000288

	/* Read Response Buffer Status Register  -- read-only */
#define PIC_READ_RESP_BUF_STATUS 0x00000290

	/* Read Response Buffer Clear Register  -- write-only */
#define PIC_READ_RESP_BUF_CLEAR 0x00000298

	/* PCI RR 0 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_0_UPPER_ADDR_MATCH 0x00000300

	/* PCI RR 0 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_0_LOWER_ADDR_MATCH 0x00000308

	/* PCI RR 1 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_1_UPPER_ADDR_MATCH 0x00000310

	/* PCI RR 1 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_1_LOWER_ADDR_MATCH 0x00000318

	/* PCI RR 2 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_2_UPPER_ADDR_MATCH 0x00000320

	/* PCI RR 2 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_2_LOWER_ADDR_MATCH 0x00000328

	/* PCI RR 3 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_3_UPPER_ADDR_MATCH 0x00000330

	/* PCI RR 3 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_3_LOWER_ADDR_MATCH 0x00000338

	/* PCI RR 4 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_4_UPPER_ADDR_MATCH 0x00000340

	/* PCI RR 4 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_4_LOWER_ADDR_MATCH 0x00000348

	/* PCI RR 5 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_5_UPPER_ADDR_MATCH 0x00000350

	/* PCI RR 5 Lower Address Match Register  -- read-only */
#define PIC_PCI_RR_5_LOWER_ADDR_MATCH 0x00000358

	/* PCI RR 6 Upper Address Match Register  -- read-only */
#define PIC_PCI_RR_6_UPPER_ADDR_MATCH 0x00000360

	/* PCI RR 6 Lower Address Match Register  -- read-only */