bridge.h

linux-2.4.29操作系统的源码

					 BRIDGE_DEV_SWAP_PMU)
#define BRIDGE_DEV_D32_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
					 BRIDGE_DEV_SWAP_DIR		| \
					 BRIDGE_DEV_PREF		| \
					 BRIDGE_DEV_PRECISE		| \
					 BRIDGE_DEV_COH			| \
					 BRIDGE_DEV_BARRIER)
#define XBRIDGE_DEV_D64_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
					 BRIDGE_DEV_COH			| \
					 BRIDGE_DEV_BARRIER)
#define BRIDGE_DEV_D64_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
					 BRIDGE_DEV_SWAP_DIR		| \
					 BRIDGE_DEV_COH			| \
					 BRIDGE_DEV_BARRIER)

/* Bridge Error Upper register bit field definition */
#define BRIDGE_ERRUPPR_DEVMASTER	(0x1 << 20)	/* Device was master */
#define BRIDGE_ERRUPPR_PCIVDEV		(0x1 << 19)	/* Virtual Req value */
#define BRIDGE_ERRUPPR_DEVNUM_SHFT	(16)
#define BRIDGE_ERRUPPR_DEVNUM_MASK	(0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
#define BRIDGE_ERRUPPR_DEVICE(err)	(((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
#define BRIDGE_ERRUPPR_ADDRMASK		(0xFFFF)

/* Bridge interrupt mode register bits definition */
#define BRIDGE_INTMODE_CLR_PKT_EN(x)	(0x1 << (x))

/* this should be written to the xbow's link_control(x) register */
#define BRIDGE_CREDIT	3

/* RRB assignment register */
#define	BRIDGE_RRB_EN	0x8	/* after shifting down */
#define	BRIDGE_RRB_DEV	0x7	/* after shifting down */
#define	BRIDGE_RRB_VDEV	0x4	/* after shifting down, 2 virtual channels */
#define	BRIDGE_RRB_PDEV	0x3	/* after shifting down, 8 devices */

#define	PIC_RRB_EN	0x8	/* after shifting down */
#define	PIC_RRB_DEV	0x7	/* after shifting down */
#define	PIC_RRB_VDEV	0x6	/* after shifting down, 4 virtual channels */
#define	PIC_RRB_PDEV	0x1	/* after shifting down, 4 devices */

/* RRB status register */
#define	BRIDGE_RRB_VALID(r)	(0x00010000<<(r))
#define	BRIDGE_RRB_INUSE(r)	(0x00000001<<(r))

/* RRB clear register */
#define	BRIDGE_RRB_CLEAR(r)	(0x00000001<<(r))

/* Defines for the virtual channels so we don't hardcode 0-3 within code */
#define VCHAN0	0	/* virtual channel 0 (ie. the "normal" channel) */
#define VCHAN1	1	/* virtual channel 1 */
#define VCHAN2	2	/* virtual channel 2 - PIC only */
#define VCHAN3	3	/* virtual channel 3 - PIC only */

/* PIC: PCI-X Read Buffer Attribute Register (RBAR) */
#define NUM_RBAR 16	/* number of RBAR registers */

/* xbox system controller declarations */
#define XBOX_BRIDGE_WID         8
#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
#define XBOX_RPS_EXISTS		1 << 6	 /* RPS bit in status register */
#define XBOX_RPS_FAIL		1 << 4	 /* RPS status bit in register */

/* ========================================================================
 */
/*
 * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
 * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
 */
/* XTALK addresses that map into Bridge Bus addr space */
#define BRIDGE_PIO32_XTALK_ALIAS_BASE	0x000040000000L
#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT	0x00007FFFFFFFL
#define BRIDGE_PIO64_XTALK_ALIAS_BASE	0x000080000000L
#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT	0x0000BFFFFFFFL
#define BRIDGE_PCIIO_XTALK_ALIAS_BASE	0x000100000000L
#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT	0x0001FFFFFFFFL

/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
#define BRIDGE_MIN_PIO_ADDR_MEM		0x00000000	/* 1G PCI memory space */
#define BRIDGE_MAX_PIO_ADDR_MEM		0x3fffffff
#define BRIDGE_MIN_PIO_ADDR_IO		0x00000000	/* 4G PCI IO space */
#define BRIDGE_MAX_PIO_ADDR_IO		0xffffffff

/* XTALK addresses that map into PCI addresses */
#define BRIDGE_PCI_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
#define BRIDGE_PCI_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT
#define BRIDGE_PCI_MEM64_BASE		BRIDGE_PIO64_XTALK_ALIAS_BASE
#define BRIDGE_PCI_MEM64_LIMIT		BRIDGE_PIO64_XTALK_ALIAS_LIMIT
#define BRIDGE_PCI_IO_BASE		BRIDGE_PCIIO_XTALK_ALIAS_BASE
#define BRIDGE_PCI_IO_LIMIT		BRIDGE_PCIIO_XTALK_ALIAS_LIMIT

/*
 * Macros for Xtalk to Bridge bus (PCI) PIO
 * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II
 * Programmer's Reference" (Revision 0.8 as of this writing).
 *
 * These are PIC bridge specific.  A separate set of macros was defined
 * because PIC deviates from Bridge/Xbridge by not supporting a big-window
 * alias for PCI I/O space, and also redefines XTALK addresses
 * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second
 * bus.
 */

/* XTALK addresses that map into PIC Bridge Bus addr space */
#define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE	0x000040000000L
#define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT	0x00007FFFFFFFL
#define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE	0x000080000000L
#define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT	0x0000BFFFFFFFL
#define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE	0x0000C0000000L
#define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT	0x0000FFFFFFFFL
#define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE	0x000100000000L
#define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT	0x00013FFFFFFFL

/* XTALK addresses that map into PCI addresses */
#define PICBRIDGE0_PCI_MEM32_BASE	PICBRIDGE0_PIO32_XTALK_ALIAS_BASE
#define PICBRIDGE0_PCI_MEM32_LIMIT	PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT
#define PICBRIDGE0_PCI_MEM64_BASE	PICBRIDGE0_PIO64_XTALK_ALIAS_BASE
#define PICBRIDGE0_PCI_MEM64_LIMIT	PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT
#define PICBRIDGE1_PCI_MEM32_BASE	PICBRIDGE1_PIO32_XTALK_ALIAS_BASE
#define PICBRIDGE1_PCI_MEM32_LIMIT	PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT
#define PICBRIDGE1_PCI_MEM64_BASE	PICBRIDGE1_PIO64_XTALK_ALIAS_BASE
#define PICBRIDGE1_PCI_MEM64_LIMIT	PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT

/*
 * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
 */
/* Bridge Bus DMA addresses */
#define BRIDGE_LOCAL_BASE		0
#define BRIDGE_DMA_MAPPED_BASE		0x40000000
#define BRIDGE_DMA_MAPPED_SIZE		0x40000000	/* 1G Bytes */
#define BRIDGE_DMA_DIRECT_BASE		0x80000000
#define BRIDGE_DMA_DIRECT_SIZE		0x80000000	/* 2G Bytes */

#define PCI32_LOCAL_BASE		BRIDGE_LOCAL_BASE

/* PCI addresses of regions decoded by Bridge for DMA */
#define PCI32_MAPPED_BASE		BRIDGE_DMA_MAPPED_BASE
#define PCI32_DIRECT_BASE		BRIDGE_DMA_DIRECT_BASE

#ifndef __ASSEMBLY__

#define IS_PCI32_LOCAL(x)	((uint64_t)(x) < PCI32_MAPPED_BASE)
#define IS_PCI32_MAPPED(x)	((uint64_t)(x) < PCI32_DIRECT_BASE && \
					(uint64_t)(x) >= PCI32_MAPPED_BASE)
#define IS_PCI32_DIRECT(x)	((uint64_t)(x) >= PCI32_MAPPED_BASE)
#define IS_PCI64(x)		((uint64_t)(x) >= PCI64_BASE)
#endif				/* __ASSEMBLY__ */

/*
 * The GIO address space.
 */
/* Xtalk to GIO PIO */
#define BRIDGE_GIO_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
#define BRIDGE_GIO_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT

#define GIO_LOCAL_BASE			BRIDGE_LOCAL_BASE

/* GIO addresses of regions decoded by Bridge for DMA */
#define GIO_MAPPED_BASE			BRIDGE_DMA_MAPPED_BASE
#define GIO_DIRECT_BASE			BRIDGE_DMA_DIRECT_BASE

#ifndef __ASSEMBLY__

#define IS_GIO_LOCAL(x)		((uint64_t)(x) < GIO_MAPPED_BASE)
#define IS_GIO_MAPPED(x)	((uint64_t)(x) < GIO_DIRECT_BASE && \
					(uint64_t)(x) >= GIO_MAPPED_BASE)
#define IS_GIO_DIRECT(x)	((uint64_t)(x) >= GIO_MAPPED_BASE)
#endif				/* __ASSEMBLY__ */

/* PCI to xtalk mapping */

/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
 * which xtalk address is accessed
 */
#define BRIDGE_DIRECT_32_SEG_SIZE	BRIDGE_DMA_DIRECT_SIZE
#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)		\
	((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +	\
		((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)

/* 64-bit address attribute masks */
#define PCI64_ATTR_TARG_MASK	0xf000000000000000
#define PCI64_ATTR_TARG_SHFT	60
#define PCI64_ATTR_PREF		(1ull << 59)
#define PCI64_ATTR_PREC		(1ull << 58)
#define PCI64_ATTR_VIRTUAL	(1ull << 57)
#define PCI64_ATTR_BAR		(1ull << 56)
#define PCI64_ATTR_SWAP		(1ull << 55)
#define PCI64_ATTR_RMF_MASK	0x00ff000000000000
#define PCI64_ATTR_RMF_SHFT	48

#ifndef __ASSEMBLY__
/* Address translation entry for mapped pci32 accesses */
typedef union ate_u {
    uint64_t		    ent;
    struct xb_ate_s {					/* xbridge */
	uint64_t		:16;
	uint64_t		addr:36;
	uint64_t		targ:4;
	uint64_t		reserved:2;
        uint64_t		swap:1;
	uint64_t		barrier:1;
	uint64_t		prefetch:1;
	uint64_t		precise:1;
	uint64_t		coherent:1;
	uint64_t		valid:1;
    } xb_field;
    struct ate_s {					/* bridge */
	uint64_t		rmf:16;
	uint64_t		addr:36;
	uint64_t		targ:4;
	uint64_t		reserved:3;
	uint64_t		barrier:1;
	uint64_t		prefetch:1;
	uint64_t		precise:1;
	uint64_t		coherent:1;
	uint64_t		valid:1;
    } field;
} ate_t;
#endif				/* __ASSEMBLY__ */

#define ATE_V		(1 << 0)
#define ATE_CO		(1 << 1)
#define ATE_PREC	(1 << 2)
#define ATE_PREF	(1 << 3)
#define ATE_BAR		(1 << 4)
#define ATE_SWAP        (1 << 5)

#define ATE_PFNSHIFT		12
#define ATE_TIDSHIFT		8
#define ATE_RMFSHIFT		48

#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
				((xid)<<ATE_TIDSHIFT) | \
				(attr)

/*
 * for xbridge, bit 29 of the pci address is the swap bit */
#define ATE_SWAPSHIFT		29
#define ATE_SWAP_ON(x)		((x) |= (1 << ATE_SWAPSHIFT))
#define ATE_SWAP_OFF(x)		((x) &= ~(1 << ATE_SWAPSHIFT))

/* extern declarations */

#ifndef __ASSEMBLY__

/* ========================================================================
 */

#ifdef	MACROFIELD_LINE
/*
 * This table forms a relation between the byte offset macros normally
 * used for ASM coding and the calculated byte offsets of the fields
 * in the C structure.
 *
 * See bridge_check.c and bridge_html.c for further details.
 */
#ifndef MACROFIELD_LINE_BITFIELD
#define MACROFIELD_LINE_BITFIELD(m)	/* ignored */
#endif

struct macrofield_s	bridge_macrofield[] =
{

    MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id)
    MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM)
    MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM)
    MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM)
    MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat)
    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N)
    MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING)
    MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper)
    MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower)
    MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK)
    MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK)
    MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout)
    MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper)
    MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR)
    MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID)
    MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR)
    MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower)
    MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword)
    MACROFIELD_LINE_BITFIELD(WIDGET_DIDN)
    MACROFIELD_LINE_BITFIELD(WIDGET_SIDN)
    MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP)
    MACROFIELD_LINE_BITFIELD(WIDGET_TNUM)
    MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT)
    MACROFIELD_LINE_BITFIELD(WIDGET_DS)
    MACROFIELD_LINE_BITFIELD(WIDGET_GBR)
    MACROFIELD_LINE_BITFIELD(WIDGET_VBPM)
    MACROFIELD_LINE_BITFIELD(WIDGET_ERROR)
    MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER)
    MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp)
    MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY)
    MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT)
    MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST)
    MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush)
    MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err)
    MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper)
    MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower)
    MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl)
    MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map)
    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID)
    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64)
    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512)
    MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF)
    MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr)
    MACROFIELD_LINE(BRIDGE_ARB, b_arb)
    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK)
    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK)
    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT)
    MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2)
    MACROFIELD_LINE_