📄 bridge.h
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#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)#define BRIDGE_CTRL_SYS_END (0x1 << 9)#define BRIDGE_CTRL_PCI_SPEED (0x3 << 4)#define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4)#define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3))#define BRIDGE_CTRL_BUS_SPEED_33 0x00#define BRIDGE_CTRL_BUS_SPEED_66 0x10#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))/* Bridge Response buffer Error Upper Register bit fields definition */#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \ (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \ BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \ (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \ BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)/* Bridge direct mapping register bits definition */#define BRIDGE_DIRMAP_W_ID_SHFT 20#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 *//* Bridge Arbitration register bits definition */#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)#define BRIDGE_ARB_FREEZE_GNT (1 << 6)#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)/* Bridge Bus time-out register bits definition */#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)/* Bridge interrupt status register bits definition */#define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45)#define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44)#define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43)#define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42)#define PIC_ISR_INT_RAM_PERR (0x1ull << 41)#define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40)#define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39)#define PIC_ISR_PCIX_TABORT (0x1ull << 38)#define PIC_ISR_PCIX_PERR (0x1ull << 37)#define PIC_ISR_PCIX_SERR (0x1ull << 36)#define PIC_ISR_PCIX_MRETRY (0x1ull << 35)#define PIC_ISR_PCIX_MTOUT (0x1ull << 34)#define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33)#define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32)#define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */#define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)#define BRIDGE_ISR_PCI_SERR (0x1 << 13)#define BRIDGE_ISR_PCI_PERR (0x1 << 12)#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)#define BRIDGE_ISR_INT_MSK (0xff << 0)#define BRIDGE_ISR_INT(x) (0x1 << (x))#define BRIDGE_ISR_LINK_ERROR \ (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \ BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \ BRIDGE_ISR_LLP_TCTY)#define BRIDGE_ISR_PCIBUS_PIOERR \ (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \ PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)#define BRIDGE_ISR_PCIBUS_ERROR \ (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \ PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \ PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \ PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \ PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \ PIC_ISR_PCIX_SPLIT_MSG_PE)#define BRIDGE_ISR_XTALK_ERROR \ (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \ BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \ BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \ BRIDGE_ISR_UNEXP_RESP)#define BRIDGE_ISR_ERRORS \ (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR)/* * List of Errors which are fatal and kill the sytem */#define BRIDGE_ISR_ERROR_FATAL \ ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \ PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \ PIC_ISR_PCIX_DA_PARITY| \ PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE )#define BRIDGE_ISR_ERROR_DUMP \ (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR)/* Bridge interrupt enable register bits definition */#define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE#define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG#define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO#define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP#define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR#define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR#define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT#define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT#define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR#define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR#define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY#define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT#define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY#define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)/* * Bridge interrupt reset register bits definition. Note, PIC can * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do * groups of them. */#define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE#define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG#define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO#define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP#define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR#define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR#define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT#define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT#define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR#define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR#define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY#define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT#define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY#define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY#define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT#define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP#define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT#define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT#define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR#define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR#define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR#define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP#define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW#define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR#define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR#define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY#define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY#define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY#define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT#define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY#define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR#define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR#define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT#define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT#define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)#define BRIDGE_IRR_ALL_CLR 0x7f#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \ BRIDGE_ISR_XREQ_FIFO_OFLOW)#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \ BRIDGE_ISR_RESP_XTLK_ERR | \ BRIDGE_ISR_XREAD_REQ_TIMEOUT)#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \ BRIDGE_ISR_BAD_XREQ_PKT | \ BRIDGE_ISR_REQ_XTLK_ERR | \ BRIDGE_ISR_INVLD_ADDR)#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \ BRIDGE_ISR_LLP_REC_CBERR | \ BRIDGE_ISR_LLP_RCTY | \ BRIDGE_ISR_LLP_TX_RETRY | \ BRIDGE_ISR_LLP_TCTY)#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \ BRIDGE_ISR_PMU_ESIZE_FAULT)#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \ BRIDGE_ISR_PCI_PARITY | \ BRIDGE_ISR_PCI_SERR | \ BRIDGE_ISR_PCI_PERR | \ BRIDGE_ISR_PCI_MST_TIMEOUT | \ BRIDGE_ISR_PCI_RETRY_CNT)#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ BRIDGE_ISR_GIO_MST_TIMEOUT)#define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR#define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \ PIC_IRR_PCIX_DA_PARITY | \ PIC_IRR_PCIX_MTOUT | \ PIC_IRR_PCIX_MRETRY | \ PIC_IRR_PCIX_SERR | \ PIC_IRR_PCIX_PERR | \ PIC_IRR_PCIX_TABORT | \ PIC_ISR_PCIX_REQ_TOUT | \ PIC_ISR_PCIX_UNEX_COMP | \ PIC_ISR_PCIX_SPLIT_TO | \ PIC_ISR_PCIX_SPLIT_EMSG | \ PIC_ISR_PCIX_SPLIT_MSG_PE)/* Bridge INT_DEV register bits definition */#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) /* Bridge interrupt(x) register bits definition */#define BRIDGE_INT_ADDR_HOST 0x0003FF00#define BRIDGE_INT_ADDR_FLD 0x000000FF/* PIC interrupt(x) register bits definition */#define PIC_INT_ADDR_FLD 0x00FF000000000000#define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff/* Bridge device(x) register bits definition */#define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28)#define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27)#define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26)#define BRIDGE_DEV_VIRTUAL_EN (1ull << 25)#define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24)#define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23)#define BRIDGE_DEV_DEV_SIZE (1ull << 22)#define BRIDGE_DEV_RT (1ull << 21)#define BRIDGE_DEV_SWAP_PMU (1ull << 20)#define BRIDGE_DEV_SWAP_DIR (1ull << 19)#define BRIDGE_DEV_PREF (1ull << 18)#define BRIDGE_DEV_PRECISE (1ull << 17)#define BRIDGE_DEV_COH (1ull << 16)#define BRIDGE_DEV_BARRIER (1ull << 15)#define BRIDGE_DEV_GBR (1ull << 14)#define BRIDGE_DEV_DEV_SWAP (1ull << 13)#define BRIDGE_DEV_DEV_IO_MEM (1ull << 12)#define BRIDGE_DEV_OFF_MASK 0x00000fff#define BRIDGE_DEV_OFF_ADDR_SHFT 20#define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \⌨️ 快捷键说明
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