bridge.h

linux-2.4.29操作系统的源码

	    bridgereg_t	    _b_int_enable;	    /* 0x00010C */
	    bridgereg_t	    _b_pad_000108;
	} _b;
    } u_int_enable;
    #define p_int_enable_64 u_int_enable._p_int_enable
    #define b_int_enable u_int_enable._b._b_int_enable

    union {
	picreg_t	    _p_int_rst_stat;	    /* 0x000110 */		
	struct {
	    bridgereg_t	    _b_int_rst_stat;	    /* 0x000114 */
	    bridgereg_t	    _b_pad_000110;
	} _b;
    } u_int_rst_stat;
    #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat
    #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat

    bridgereg_t		    b_int_mode;		    /* 0x00011C */
    bridgereg_t		    _pad_000118;

    bridgereg_t		    b_int_device;	    /* 0x000124 */
    bridgereg_t		    _pad_000120;

    bridgereg_t		    b_int_host_err;	    /* 0x00012C */
    bridgereg_t		    _pad_000128;

    union {
	picreg_t	    _p_int_addr[8];	    /* 0x0001{30,,,68} */
	struct {
	    bridgereg_t	    addr;		    /* 0x0001{34,,,6C} */
	    bridgereg_t	    _b_pad;
	} _b[8];
    } u_int_addr;
    #define p_int_addr_64 u_int_addr._p_int_addr
    #define b_int_addr u_int_addr._b

    union {
	picreg_t	    _p_err_int_view;	    /* 0x000170 */
	struct {
	    bridgereg_t	    _b_err_int_view;	    /* 0x000174 */
	    bridgereg_t	    _b_pad_000170;
	} _b;
    } u_err_int_view;
    #define p_err_int_view_64 u_err_int_view._p_err_int_view
    #define b_err_int_view u_err_int_view._b._b_err_int_view

    union {
	picreg_t	    _p_mult_int;	    /* 0x000178 */
	struct {
	    bridgereg_t	    _b_mult_int;	    /* 0x00017C */
	    bridgereg_t	    _b_pad_000178;
	} _b;
    } u_mult_int;
    #define p_mult_int_64 u_mult_int._p_mult_int
    #define b_mult_int u_mult_int._b._b_mult_int

    struct {
	bridgereg_t	    intr;		    /* 0x0001{84,,,BC} */
	bridgereg_t	    __pad;
    } b_force_always[8];

    struct {
	bridgereg_t	    intr;		    /* 0x0001{C4,,,FC} */
	bridgereg_t	    __pad;
    } b_force_pin[8];

    /* 0x000200-0x0003FF -- Device */
    struct {
	bridgereg_t	    reg;		    /* 0x0002{04,,,3C} */
	bridgereg_t	    __pad;
    } b_device[8];

    struct {
	bridgereg_t	    reg;		    /* 0x0002{44,,,7C} */
	bridgereg_t	    __pad;
    } b_wr_req_buf[8];

    struct {
	bridgereg_t	    reg;		    /* 0x0002{84,,,8C} */
	bridgereg_t	    __pad;
    } b_rrb_map[2];
    #define b_even_resp	b_rrb_map[0].reg	    /* 0x000284 */
    #define b_odd_resp	b_rrb_map[1].reg	    /* 0x00028C */

    bridgereg_t		    b_resp_status;	    /* 0x000294 */
    bridgereg_t		    _pad_000290;

    bridgereg_t		    b_resp_clear;	    /* 0x00029C */
    bridgereg_t		    _pad_000298;

    bridgereg_t		    _pad_0002A0[24];

    /* Xbridge/PIC only */
    union {
	struct {
	    picreg_t	    lower;		    /* 0x0003{08,,,F8} */
	    picreg_t	    upper;		    /* 0x0003{00,,,F0} */
	} _p[16];
	struct {
	    bridgereg_t	    upper;		    /* 0x0003{04,,,F4} */
	    bridgereg_t	    _b_pad1;
	    bridgereg_t	    lower;		    /* 0x0003{0C,,,FC} */
	    bridgereg_t	    _b_pad2;
	} _b[16];
    } u_buf_addr_match;
    #define p_buf_addr_match_64 u_buf_addr_match._p
    #define b_buf_addr_match u_buf_addr_match._b

    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
    struct {
	bridgereg_t	    flush_w_touch;	    /* 0x000{404,,,5C4} */
	bridgereg_t	    __pad1;
	bridgereg_t	    flush_wo_touch;	    /* 0x000{40C,,,5CC} */
	bridgereg_t	    __pad2;
	bridgereg_t	    inflight;		    /* 0x000{414,,,5D4} */
	bridgereg_t	    __pad3;
	bridgereg_t	    prefetch;		    /* 0x000{41C,,,5DC} */
	bridgereg_t	    __pad4;
	bridgereg_t	    total_pci_retry;	    /* 0x000{424,,,5E4} */
	bridgereg_t	    __pad5;
	bridgereg_t	    max_pci_retry;	    /* 0x000{42C,,,5EC} */
	bridgereg_t	    __pad6;
	bridgereg_t	    max_latency;	    /* 0x000{434,,,5F4} */
	bridgereg_t	    __pad7;
	bridgereg_t	    clear_all;		    /* 0x000{43C,,,5FC} */
	bridgereg_t	    __pad8;
    } b_buf_count[8];

    /*
     * "PCI/X registers that are specific to PIC".   See pic.h.
     */

    /* 0x000600-0x0009FF -- PCI/X registers */
    picreg_t		    p_pcix_bus_err_addr_64;     /* 0x000600 */
    picreg_t		    p_pcix_bus_err_attr_64;     /* 0x000608 */
    picreg_t		    p_pcix_bus_err_data_64;     /* 0x000610 */
    picreg_t		    p_pcix_pio_split_addr_64;	/* 0x000618 */
    picreg_t		    p_pcix_pio_split_attr_64;	/* 0x000620 */
    picreg_t		    p_pcix_dma_req_err_attr_64; /* 0x000628 */
    picreg_t		    p_pcix_dma_req_err_addr_64;	/* 0x000630 */
    picreg_t		    p_pcix_timeout_64;		/* 0x000638 */

    picreg_t		    _pad_000600[120];

    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
    struct {
    	picreg_t	    p_buf_attr;		    /* 0X000{A08,,,AF8} */
    	picreg_t	    p_buf_addr;		    /* 0x000{A00,,,AF0} */
    } p_pcix_read_buf_64[16];

    struct {
	picreg_t	    p_buf_attr;		    /* 0x000{B08,,,BE8} */
	picreg_t	    p_buf_addr;		    /* 0x000{B00,,,BE0} */
	picreg_t	    __pad1;		    /* 0x000{B18,,,BF8} */
	picreg_t	    p_buf_valid;	    /* 0x000{B10,,,BF0} */
    } p_pcix_write_buf_64[8];

    /* 
     * end "PCI/X registers that are specific to PIC"
     */

    char		    _pad_000c00[0x010000 - 0x000c00];

    /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */
    /*
     * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128.
     * Make enough room for the Xbridge/PIC ATE's and depend on runtime
     * checks to limit access to bridge ATE's.
     *
     * In [X]bridge the internal ATE Ram is writen as double words only,
     * but due to internal design issues it is read back as single words. 
     * i.e:
     *   b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd
     */
    union {
	bridge_ate_t	    wr;	/* write-only */    /* 0x01{0000,,,1FF8} */
	struct {
	    bridgereg_t	    rd; /* read-only */     /* 0x01{0004,,,1FFC} */
	    bridgereg_t	    _p_pad;
	} hi;
    } b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
    #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd

    /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */
    struct {
	bridgereg_t	    rd; /* read-only */	    /* 0x01{2004,,,3FFC} */
	bridgereg_t	    _p_pad;
    } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];

    char		    _pad_014000[0x18000 - 0x014000];

    /* 0x18000-0x197F8 -- PIC Write Request Ram */
				/* 0x18000 - 0x187F8 */
    picreg_t		    p_wr_req_lower[PIC_WR_REQ_BUFSIZE];
				/* 0x18800 - 0x18FF8 */
    picreg_t		    p_wr_req_upper[PIC_WR_REQ_BUFSIZE];
				/* 0x19000 - 0x197F8 */
    picreg_t		    p_wr_req_parity[PIC_WR_REQ_BUFSIZE];

    char		    _pad_019800[0x20000 - 0x019800];

    /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
    union {				/* make all access sizes available. */
	uchar_t		    c[0x1000 / 1];	    /* 0x02{0000,,,7FFF} */
	uint16_t	    s[0x1000 / 2];	    /* 0x02{0000,,,7FFF} */
	uint32_t	    l[0x1000 / 4];	    /* 0x02{0000,,,7FFF} */
	uint64_t	    d[0x1000 / 8];	    /* 0x02{0000,,,7FFF} */
	union {
	    uchar_t	    c[0x100 / 1];
	    uint16_t	    s[0x100 / 2];
	    uint32_t	    l[0x100 / 4];
	    uint64_t	    d[0x100 / 8];
	} f[8];
    } b_type0_cfg_dev[8];			    /* 0x02{0000,,,7FFF} */

    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
    union {				/* make all access sizes available. */
	uchar_t		    c[0x1000 / 1];
	uint16_t	    s[0x1000 / 2];
	uint32_t	    l[0x1000 / 4];
	uint64_t	    d[0x1000 / 8];
        union {
            uchar_t         c[0x100 / 1];
            uint16_t        s[0x100 / 2];
            uint32_t        l[0x100 / 4];
            uint64_t        d[0x100 / 8];
	} f[8];
    } b_type1_cfg;				    /* 0x028000-0x029000 */

    char		    _pad_029000[0x007000];  /* 0x029000-0x030000 */

    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
    union {
	uchar_t		    c[8 / 1];
	uint16_t	    s[8 / 2];
	uint32_t	    l[8 / 4];
	uint64_t	    d[8 / 8];
    } b_pci_iack;				    /* 0x030000-0x030007 */

    uchar_t		    _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */

    /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */
    bridge_ate_t	    b_ext_ate_ram[0x10000];

    /* 0x100000-0x1FFFFF -- Reserved */
    char		    _pad_100000[0x200000-0x100000];

    /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */
    union {				/* make all access sizes available. */
	uchar_t		    c[0x100000 / 1];
	uint16_t	    s[0x100000 / 2];
	uint32_t	    l[0x100000 / 4];
	uint64_t	    d[0x100000 / 8];
    } b_devio_raw[10];

    /* b_devio macro is a bit strange; it reflects the
     * fact that the Bridge ASIC provides 2M for the
     * first two DevIO windows and 1M for the other six.
     */
    #define b_devio(n)	b_devio_raw[((n)<2)?(n*2):(n+2)]

    /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */
    union {				/* make all access sizes available. */
	uchar_t		    c[0x400000 / 1];	/* read-only */
	uint16_t	    s[0x400000 / 2];	/* read-write */
	uint32_t	    l[0x400000 / 4];	/* read-only */
	uint64_t	    d[0x400000 / 8];	/* read-only */
    } b_external_flash;
} bridge_t;

#define berr_field	berr_un.berr_st
#endif				/* __ASSEMBLY__ */

/*
 * The values of these macros can and should be crosschecked
 * regularly against the offsets of the like-named fields
 * within the "bridge_t" structure above.
 */

/* Byte offset macros for Bridge internal registers */

#define BRIDGE_WID_ID		WIDGET_ID
#define BRIDGE_WID_STAT		WIDGET_STATUS
#define BRIDGE_WID_ERR_UPPER	WIDGET_ERR_UPPER_ADDR
#define BRIDGE_WID_ERR_LOWER	WIDGET_ERR_LOWER_ADDR
#define BRIDGE_WID_CONTROL	WIDGET_CONTROL
#define BRIDGE_WID_REQ_TIMEOUT	WIDGET_REQ_TIMEOUT
#define BRIDGE_WID_INT_UPPER	WIDGET_INTDEST_UPPER_ADDR
#define BRIDGE_WID_INT_LOWER	WIDGET_INTDEST_LOWER_ADDR
#define BRIDGE_WID_ERR_CMDWORD	WIDGET_ERR_CMD_WORD
#define BRIDGE_WID_LLP		WIDGET_LLP_CFG
#define BRIDGE_WID_TFLUSH	WIDGET_TFLUSH

#define BRIDGE_WID_AUX_ERR	0x00005C	/* Aux Error Command Word */
#define BRIDGE_WID_RESP_UPPER	0x000064	/* Response Buf Upper Addr */
#define BRIDGE_WID_RESP_LOWER	0x00006C	/* Response Buf Lower Addr */
#define BRIDGE_WID_TST_PIN_CTRL 0x000074	/* Test pin control */

#define BRIDGE_DIR_MAP		0x000084	/* Direct Map reg */

/* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */
#define BRIDGE_RAM_PERR 	0x000094	/* SSRAM Parity Error */
#define BRIDGE_MAP_FAULT	0x000094	/* Map Fault */

#define BRIDGE_ARB		0x0000A4	/* Arbitration Priority reg */

#define BRIDGE_NIC		0x0000B4	/* Number In A Can */

#define BRIDGE_BUS_TIMEOUT	0x0000C4	/* Bus Timeout Register */
#define BRIDGE_PCI_BUS_TIMEOUT	BRIDGE_BUS_TIMEOUT
#define BRIDGE_PCI_CFG		0x0000CC	/* PCI Type 1 Config reg */
#define BRIDGE_PCI_ERR_UPPER	0x0000D4	/* PCI error Upper Addr */
#define BRIDGE_PCI_ERR_LOWER	0x0000DC	/* PCI error Lower Addr */

#define BRIDGE_INT_STATUS	0x000104	/* Interrupt Status */
#define BRIDGE_INT_ENABLE	0x00010C	/* Interrupt Enables */
#define BRIDGE_INT_RST_STAT	0x000114	/* Reset Intr Status */
#define BRIDGE_INT_MODE		0x00011C	/* Interrupt Mode */
#define BRIDGE_INT_DEVICE	0x000124	/* Interrupt Device */
#define BRIDGE_INT_HOST_ERR	0x00012C	/* Host Error Field */

#define BRIDGE_INT_ADDR0	0x000134	/* Host Address Reg */
#define BRIDGE_INT_ADDR_OFF	0x000008	/* Host Addr offset (1..7) */
#define BRIDGE_INT_ADDR(x)	(BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)

#define BRIDGE_INT_VIEW		0x000174	/* Interrupt view */
#define BRIDGE_MULTIPLE_INT	0x00017c	/* Multiple interrupt occurred */

#define BRIDGE_FORCE_ALWAYS0	0x000184	/* Force an interrupt (always)*/
#define BRIDGE_FORCE_ALWAYS_OFF 0x000008	/* Force Always offset */
#define BRIDGE_FORCE_ALWAYS(x)  (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF)

#define BRIDGE_FORCE_PIN0	0x0001c4	/* Force an interrupt */