bridge.h

linux-2.4.29操作系统的源码

/* $Id$
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
 */
#ifndef _ASM_SN_PCI_BRIDGE_H
#define _ASM_SN_PCI_BRIDGE_H


/*
 * bridge.h - header file for bridge chip and bridge portion of xbridge chip
 *
 * Also including offsets for unique PIC registers.
 * The PIC asic is a follow-on to Xbridge and most of its registers are
 * identical to those of Xbridge.  PIC is different than Xbridge in that
 * it will accept 64 bit register access and that, in some cases, data
 * is kept in bits 63:32.   PIC registers that are identical to Xbridge
 * may be accessed identically to the Xbridge registers, allowing for lots
 * of code reuse.  Here are the access rules as described in the PIC
 * manual:
 * 
 * 	o Read a word on a DW boundary returns D31:00 of reg.
 * 	o Read a DW on a DW boundary returns D63:00 of reg.
 * 	o Write a word on a DW boundary loads D31:00 of reg.
 * 	o Write a DW on a DW boundary loads D63:00 of reg.
 * 	o No support for word boundary access that is not double word
 *           aligned.
 * 
 * So we can reuse a lot of bridge_s for PIC.  In bridge_s are included
 * #define tags and unions for 64 bit access to PIC registers.
 * For a detailed PIC register layout see pic.h.
 */

#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/sn/xtalk/xwidget.h>
#include <asm/sn/pci/pic.h>
#else
#include <linux/config.h>
#include <xtalk/xwidget.h>
#include <pci/pic.h>
#endif

/* I/O page size */

#if PAGE_SIZE == 4096
#define IOPFNSHIFT		12	/* 4K per mapped page */
#else
#define IOPFNSHIFT		14	/* 16K per mapped page */
#endif				/* _PAGESZ */

#define IOPGSIZE		(1 << IOPFNSHIFT)
#define IOPG(x)			((x) >> IOPFNSHIFT)
#define IOPGOFF(x)		((x) & (IOPGSIZE-1))

/* Bridge RAM sizes */

#define BRIDGE_INTERNAL_ATES	128
#define XBRIDGE_INTERNAL_ATES	1024

#define BRIDGE_ATE_RAM_SIZE     (BRIDGE_INTERNAL_ATES<<3)	/* 1kB ATE */
#define XBRIDGE_ATE_RAM_SIZE    (XBRIDGE_INTERNAL_ATES<<3)	/* 8kB ATE */

#define PIC_WR_REQ_BUFSIZE      256

#define BRIDGE_CONFIG_BASE	0x20000		/* start of bridge's */
						/* map to each device's */
						/* config space */
#define BRIDGE_CONFIG1_BASE	0x28000		/* type 1 device config space */
#define BRIDGE_CONFIG_END	0x30000
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000		/* each map == 4k */

#define BRIDGE_SSRAM_512K	0x00080000	/* 512kB */
#define BRIDGE_SSRAM_128K	0x00020000	/* 128kB */
#define BRIDGE_SSRAM_64K	0x00010000	/* 64kB */
#define BRIDGE_SSRAM_0K		0x00000000	/* 0kB */

/* ========================================================================
 *    Bridge address map
 */

#ifndef __ASSEMBLY__

#ifdef __cplusplus
extern "C" {
#endif

/*
 * All accesses to bridge hardware registers must be done
 * using 32-bit loads and stores.
 */
typedef uint32_t	bridgereg_t;

typedef uint64_t	bridge_ate_t;

/* pointers to bridge ATEs
 * are always "pointer to volatile"
 */
typedef volatile bridge_ate_t  *bridge_ate_p;

/*
 * It is generally preferred that hardware registers on the bridge
 * are located from C code via this structure.
 *
 * Generated from Bridge spec dated 04oct95
 */


/*
 * pic_widget_cfg_s is a local definition of widget_cfg_t but with
 * a union of 64bit & 32bit registers, since PIC has 64bit widget
 * registers but BRIDGE and XBRIDGE have 32bit.	 PIC registers that
 * have valid bits (ie. not just reserved) in the upper 32bits are
 * defined as a union so we can access them as 64bit for PIC and
 * as 32bit for BRIDGE and XBRIDGE.
 */ 
typedef volatile struct pic_widget_cfg_s {
    bridgereg_t		    _b_wid_id;		    /* 0x000004 */
    bridgereg_t		    _pad_000000;

    union {
	picreg_t	    _p_wid_stat;	    /* 0x000008 */
	struct {
	    bridgereg_t	    _b_wid_stat;	    /* 0x00000C */
	    bridgereg_t	    _b_pad_000008;
	} _b;
    } u_wid_stat;
    #define __p_wid_stat_64 u_wid_stat._p_wid_stat
    #define __b_wid_stat u_wid_stat._b._b_wid_stat

    bridgereg_t		    _b_wid_err_upper;	    /* 0x000014 */
    bridgereg_t		    _pad_000010;

    union {
	picreg_t	    _p_wid_err_lower;	    /* 0x000018 */
	struct {
	    bridgereg_t	    _b_wid_err_lower;	    /* 0x00001C */
	    bridgereg_t	    _b_pad_000018;
	} _b;
    } u_wid_err_lower;
    #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower
    #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower

    union {
	picreg_t	    _p_wid_control;	    /* 0x000020 */
	struct {
	    bridgereg_t	    _b_wid_control;	    /* 0x000024 */
	    bridgereg_t	    _b_pad_000020;
	} _b;
    } u_wid_control;
    #define __p_wid_control_64 u_wid_control._p_wid_control
    #define __b_wid_control u_wid_control._b._b_wid_control

    bridgereg_t		    _b_wid_req_timeout;	    /* 0x00002C */
    bridgereg_t		    _pad_000028;

    bridgereg_t		    _b_wid_int_upper;	    /* 0x000034 */
    bridgereg_t		    _pad_000030;

    union {
	picreg_t	    _p_wid_int_lower;	    /* 0x000038 */
	struct {
	    bridgereg_t	    _b_wid_int_lower;	    /* 0x00003C */
	    bridgereg_t	    _b_pad_000038;
	} _b;
    } u_wid_int_lower;
    #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower
    #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower

    bridgereg_t		    _b_wid_err_cmdword;	    /* 0x000044 */
    bridgereg_t		    _pad_000040;

    bridgereg_t		    _b_wid_llp;		    /* 0x00004C */
    bridgereg_t		    _pad_000048;

    bridgereg_t		    _b_wid_tflush;	    /* 0x000054 */
    bridgereg_t		    _pad_000050;
} pic_widget_cfg_t;

/*
 * BRIDGE, XBRIDGE, PIC register definitions.  NOTE: Prior to PIC, registers
 * were a 32bit quantity and double word aligned (and only accessible as a
 * 32bit word.  PIC registers are 64bits and accessible as words or double
 * words.  PIC registers that have valid bits (ie. not just reserved) in the
 * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit
 * bridgereg_t so we can access them both ways.
 *
 * It is generally preferred that hardware registers on the bridge are
 * located from C code via this structure.
 *
 * Generated from Bridge spec dated 04oct95
 */

typedef volatile struct bridge_s {

    /* 0x000000-0x00FFFF -- Local Registers */

    /* 0x000000-0x000057 -- Standard Widget Configuration */
    union {
	widget_cfg_t	    xtalk_widget_def;	    /* 0x000000 */
	pic_widget_cfg_t    local_widget_def;	    /* 0x000000 */
    } u_wid;

    /* 32bit widget register access via the widget_cfg_t */
    #define b_widget u_wid.xtalk_widget_def

    /* 32bit widget register access via the pic_widget_cfg_t */
    #define b_wid_id u_wid.local_widget_def._b_wid_id
    #define b_wid_stat u_wid.local_widget_def.__b_wid_stat
    #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper
    #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower
    #define b_wid_control u_wid.local_widget_def.__b_wid_control
    #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout
    #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper
    #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower
    #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword
    #define b_wid_llp u_wid.local_widget_def._b_wid_llp
    #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush

    /* 64bit widget register access via the pic_widget_cfg_t */
    #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64
    #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64
    #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64
    #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64

    /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
    bridgereg_t             b_wid_aux_err;          /* 0x00005C */
    bridgereg_t             _pad_000058;

    bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
    bridgereg_t             _pad_000060;

    union {
        picreg_t            _p_wid_resp_lower;      /* 0x000068 */
        struct {
            bridgereg_t     _b_wid_resp_lower;      /* 0x00006C */
            bridgereg_t     _b_pad_000068;
        } _b;
    } u_wid_resp_lower;
    #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower
    #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower

    bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
    bridgereg_t             _pad_000070;

    union {
        picreg_t            _p_addr_lkerr;          /* 0x000078 */
        struct {
            bridgereg_t     _b_pad_00007C;
            bridgereg_t     _b_pad_000078;
        } _b;
    } u_addr_lkerr;
    #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr

    /* 0x000080-0x00008F -- PMU */
    bridgereg_t		    b_dir_map;		    /* 0x000084 */
    bridgereg_t		    _pad_000080;

    bridgereg_t		    _pad_00008C;
    bridgereg_t		    _pad_000088;

    /* 0x000090-0x00009F -- SSRAM */
    bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
    bridgereg_t		    _pad_000090;
    #define b_ram_perr  b_ram_perr_or_map_fault     /* Bridge */
    #define b_map_fault b_ram_perr_or_map_fault     /* Xbridge & PIC */

    bridgereg_t		    _pad_00009C;
    bridgereg_t		    _pad_000098;

    /* 0x0000A0-0x0000AF -- Arbitration */
    bridgereg_t		    b_arb;		    /* 0x0000A4 */
    bridgereg_t		    _pad_0000A0;

    bridgereg_t		    _pad_0000AC;
    bridgereg_t		    _pad_0000A8;

    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
    union {
	picreg_t	    _p_ate_parity_err;	    /* 0x0000B0 */
	struct {
	    bridgereg_t	    _b_nic;		    /* 0x0000B4 */
	    bridgereg_t	    _b_pad_0000B0;
	} _b;
    } u_ate_parity_err_or_nic;
    #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err
    #define b_nic u_ate_parity_err_or_nic._b._b_nic

    bridgereg_t		    _pad_0000BC;
    bridgereg_t		    _pad_0000B8;

    /* 0x0000C0-0x0000FF -- PCI/GIO */
    bridgereg_t		    b_bus_timeout;	    /* 0x0000C4 */
    bridgereg_t		    _pad_0000C0;
    #define b_pci_bus_timeout b_bus_timeout

    bridgereg_t		    b_pci_cfg;		    /* 0x0000CC */
    bridgereg_t		    _pad_0000C8;

    bridgereg_t		    b_pci_err_upper;	    /* 0x0000D4 */
    bridgereg_t		    _pad_0000D0;
    #define b_gio_err_upper b_pci_err_upper

    union {
	picreg_t	    _p_pci_err_lower;	    /* 0x0000D8 */
	struct {
	    bridgereg_t	    _b_pci_err_lower;	    /* 0x0000DC */
	    bridgereg_t	    _b_pad_0000D8;
	} _b;
    } u_pci_err_lower;
    #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower
    #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower
    #define b_gio_err_lower b_pci_err_lower

    bridgereg_t		    _pad_0000E0[8];

    /* 0x000100-0x0001FF -- Interrupt */
    union {
	picreg_t	    _p_int_status;	    /* 0x000100 */		
	struct {
	    bridgereg_t	    _b_int_status;	    /* 0x000104 */
	    bridgereg_t	    _b_pad_000100;
	} _b;
    } u_int_status;
    #define p_int_status_64 u_int_status._p_int_status
    #define b_int_status u_int_status._b._b_int_status

    union {
	picreg_t	    _p_int_enable;	    /* 0x000108 */		
	struct {