📄 pcibr_private.h
字号:
void *bs_allocated_ate_res;/* resource struct allocated */ short bs_int_ate_size; /* number of internal ates */ short bs_bridge_type; /* see defines above */ short bs_bridge_mode; /* see defines above */ int bs_rev_num; /* revision number of Bridge */ /* bs_dma_flags are the forced dma flags used on all DMAs. Used for * working around ASIC rev issues and protocol specific requirements */ unsigned bs_dma_flags; /* forced DMA flags */ moduleid_t bs_moduleid; /* io brick moduleid */ short bs_bricktype; /* io brick type */ /* * Lock used primarily to get mutual exclusion while managing any * bridge resources.. */ spinlock_t bs_lock; vertex_hdl_t bs_noslot_conn; /* NO-SLOT connection point */ pcibr_info_t bs_noslot_info; struct pcibr_soft_slot_s { /* information we keep about each CFG slot */ /* some devices (ioc3 in non-slotted * configurations, sometimes) make use * of more than one REQ/GNT/INT* signal * sets. The slot corresponding to the * IDSEL that the device responds to is * called the host slot; the slot * numbers that the device is stealing * REQ/GNT/INT bits from are known as * the guest slots. */ int has_host; pciio_slot_t host_slot; vertex_hdl_t slot_conn; /* PCI Hot-Plug status word */ int slot_status; /* Potentially several connection points * for this slot. bss_ninfo is how many, * and bss_infos is a pointer to * an array pcibr_info_t values (which are * pointers to pcibr_info structs, stored * as device_info in connection ponts). */ int bss_ninfo; pcibr_info_h bss_infos; /* Temporary Compatibility Macros, for * stuff that has moved out of bs_slot * and into the info structure. These * will go away when their users have * converted over to multifunction- * friendly use of bss_{ninfo,infos}. */#define bss_vendor_id bss_infos[0]->f_vendor#define bss_device_id bss_infos[0]->f_device#define bss_window bss_infos[0]->f_window#define bssw_space w_space#define bssw_base w_base#define bssw_size w_size /* Where is DevIO(x) pointing? */ /* bssd_space is NONE if it is not assigned. */ struct { pciio_space_t bssd_space; iopaddr_t bssd_base; int bssd_ref_cnt; } bss_devio; /* Shadow value for Device(x) register, * so we don't have to go to the chip. */ bridgereg_t bss_device; /* Number of sets on GBR/REALTIME bit outstanding * Used by Priority I/O for tracking reservations */ int bss_pri_uctr; /* Number of "uses" of PMU, 32-bit direct, * and 64-bit direct DMA (0:none, <0: trans, * >0: how many dmamaps). Device(x) bits * controlling attribute of each kind of * channel can't be changed by dmamap_alloc * or dmatrans if the controlling counter * is nonzero. dmatrans is forever. */ int bss_pmu_uctr; int bss_d32_uctr; int bss_d64_uctr; /* When the contents of mapping configuration * information is locked down by dmatrans, * repeated checks of the same flags should * be shortcircuited for efficiency. */ iopaddr_t bss_d64_base; unsigned bss_d64_flags; iopaddr_t bss_d32_base; unsigned bss_d32_flags; /* Shadow information used for implementing * Bridge Hardware WAR #484930 */ atomic_t bss_ext_ates_active; volatile unsigned *bss_cmd_pointer; unsigned bss_cmd_shadow; } bs_slot[8]; pcibr_intr_bits_f *bs_intr_bits; /* PIC PCI-X Read Buffer Management : * bs_pcix_num_funcs: the total number of PCI-X functions * on the bus * bs_pcix_split_tot: total number of outstanding split * transactions requested by all functions on the bus * bs_pcix_rbar_percent_allowed: the percentage of the * total number of buffers a function requested that are * available to it, not including the 1 RBAR guaranteed * to it. * bs_pcix_rbar_inuse: number of RBARs in use. * bs_pcix_rbar_avail: number of RBARs available. NOTE: * this value can go negative if we oversubscribe the * RBARs. (i.e. We have 16 RBARs but 17 functions). */ int bs_pcix_num_funcs; int bs_pcix_split_tot; int bs_pcix_rbar_percent_allowed; int bs_pcix_rbar_inuse; int bs_pcix_rbar_avail; /* RRB MANAGEMENT * bs_rrb_fixed: bitmap of slots whose RRB * allocations we should not "automatically" change * bs_rrb_avail: number of RRBs that have not * been allocated or reserved for {even,odd} slots * bs_rrb_res: number of RRBs currently reserved for the * use of the index slot number * bs_rrb_res_dflt: number of RRBs reserved at boot * time for the use of the index slot number * bs_rrb_valid: number of RRBs currently marked valid * for the indexed slot/vchan number; array[slot][vchan] * bs_rrb_valid_dflt: number of RRBs marked valid at boot * time for the indexed slot/vchan number; array[slot][vchan] */ int bs_rrb_fixed; int bs_rrb_avail[2]; int bs_rrb_res[8]; int bs_rrb_res_dflt[8]; int bs_rrb_valid[8][4]; int bs_rrb_valid_dflt[8][4]; struct { /* Each Bridge interrupt bit has a single XIO * interrupt channel allocated. */ xtalk_intr_t bsi_xtalk_intr; /* * A wrapper structure is associated with each * Bridge interrupt bit. */ struct pcibr_intr_wrap_s bsi_pcibr_intr_wrap; } bs_intr[8]; xtalk_intr_t bsi_err_intr; /* * We stash away some information in this structure on getting * an error interrupt. This information is used during PIO read/ * write error handling. * * As it stands now, we do not re-enable the error interrupt * till the error is resolved. Error resolution happens either at * bus error time for PIO Read errors (~100 microseconds), or at * the scheduled timeout time for PIO write errors (~milliseconds). * If this delay causes problems, we may need to move towards * a different scheme.. * * Note that there is no locking while looking at this data structure. * There should not be any race between bus error code and * error interrupt code.. will look into this if needed. * * NOTE: The above discussion of error interrupt processing is * no longer true. Whether it should again be true, is * being looked into. */ struct br_errintr_info { int bserr_toutcnt;#ifdef LATER toid_t bserr_toutid; /* Timeout started by errintr */#endif /* LATER */ iopaddr_t bserr_addr; /* Address where error occured */ uint64_t bserr_intstat; /* interrupts active at error dump */ } bs_errinfo; /* * PCI Bus Space allocation data structure. * * The resource mapping functions rmalloc() and rmfree() are used * to manage the PCI bus I/O, small window, and memory address * spaces. * * This info is used to assign PCI bus space addresses to cards * via their BARs and to the callers of the pcibr_piospace_alloc() * interface. * * Users of the pcibr_piospace_alloc() interface, such as the VME * Universe chip, need PCI bus space that is not acquired by BARs. * Most of these users need "large" amounts of PIO space (typically * in Megabytes), and they generally tend to take once and never * release. */ struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ struct pciio_win_map_s bs_swin_map; /* Small window addr space */ struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ struct resource bs_io_win_root_resource; /* I/O addr space */ struct resource bs_swin_root_resource; /* Small window addr space */ struct resource bs_mem_win_root_resource; /* Memory addr space */ int bs_bus_addr_status; /* Bus space status */#define PCIBR_BUS_ADDR_MEM_FREED 1 /* Reserved PROM mem addr freed */#define PCIBR_BUS_ADDR_IO_FREED 2 /* Reserved PROM I/O addr freed */ struct bs_errintr_stat_s { uint32_t bs_errcount_total; uint32_t bs_lasterr_timestamp; uint32_t bs_lasterr_snapshot; } bs_errintr_stat[PCIBR_ISR_MAX_ERRS]; /* * Bridge-wide endianness control for * large-window PIO mappings * * These fields are set to PCIIO_BYTE_SWAP * or PCIIO_WORD_VALUES once the swapper * has been configured, one way or the other, * for the direct windows. If they are zero, * nobody has a PIO mapping through that window, * and the swapper can be set either way. */ unsigned bs_pio_end_io; unsigned bs_pio_end_mem;};#define PCIBR_ERRTIME_THRESHOLD (100)#define PCIBR_ERRRATE_THRESHOLD (100)/* * pcibr will respond to hints dropped in its vertex * using the following structure. */struct pcibr_hints_s { /* ph_host_slot is actually +1 so "0" means "no host" */ pciio_slot_t ph_host_slot[8]; /* REQ/GNT/INT in use by ... */ unsigned ph_rrb_fixed; /* do not change RRB allocations */ unsigned ph_hands_off; /* prevent further pcibr operations */ rrb_alloc_funct_t rrb_alloc_funct; /* do dynamic rrb allocation */ pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */};/* * Number of bridge non-fatal error interrupts we can see before * we decide to disable that interrupt. */#define PCIBR_ERRINTR_DISABLE_LEVEL 10000/* ===================================================================== * Bridge (pcibr) state management functions * * pcibr_soft_get is here because we do it in a lot * of places and I want to make sure they all stay * in step with each other. * * pcibr_soft_set is here because I want it to be * closely associated with pcibr_soft_get, even * though it is only called in one place. */#define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v)))#define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i)))/* * mem alloc/free macros */#define NEWAf(ptr,n,f) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr))))#define NEWA(ptr,n) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr))))#define DELA(ptr,n) (kfree(ptr))#define NEWf(ptr,f) NEWAf(ptr,1,f)#define NEW(ptr) NEWA(ptr,1)#define DEL(ptr) DELA(ptr,1)/* * Additional PIO spaces per slot are * recorded in this structure. */struct pciio_piospace_s { pciio_piospace_t next; /* another space for this device */ char free; /* 1 if free, 0 if in use */ pciio_space_t space; /* Which space is in use */ iopaddr_t start; /* Starting address of the PIO space */ size_t count; /* size of PIO space */};/* Use io spin locks. This ensures that all the PIO writes from a particular * CPU to a particular IO device are synched before the start of the next * set of PIO operations to the same device. */#ifdef PCI_LATER#define pcibr_lock(pcibr_soft) io_splock(pcibr_soft->bs_lock)#define pcibr_unlock(pcibr_soft, s) io_spunlock(pcibr_soft->bs_lock,s)#else#define pcibr_lock(pcibr_soft) 1#define pcibr_unlock(pcibr_soft, s) #endif /* PCI_LATER */#define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps))#define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF)#define PCIBR_D32_BASE_UNSET (0xFFFFFFFF)#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev"#define PCIBR_SOFT_LIST 1#if PCIBR_SOFT_LISTtypedef struct pcibr_list_s *pcibr_list_p;struct pcibr_list_s { pcibr_list_p bl_next; pcibr_soft_t bl_soft; vertex_hdl_t bl_vhdl;};#endif /* PCIBR_SOFT_LIST */// Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot.#define DEV_PER_WIDGET (2*2*8)struct sn_flush_device_list { int bus; int pin; struct bar_list { unsigned long start; unsigned long end; } bar_list[PCI_ROM_RESOURCE]; unsigned long force_int_addr; volatile unsigned long flush_addr; spinlock_t flush_lock;};struct sn_flush_nasid_entry { struct sn_flush_device_list **widget_p; unsigned long iio_itte1; unsigned long iio_itte2; unsigned long iio_itte3; unsigned long iio_itte4; unsigned long iio_itte5; unsigned long iio_itte6; unsigned long iio_itte7;};#endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -