router.h

linux-2.4.29操作系统的源码

/* $Id$
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_IA64_SN_ROUTER_H
#define _ASM_IA64_SN_ROUTER_H

/*
 * Router Register definitions
 *
 * Macro argument _L always stands for a link number (1 to 8, inclusive).
 */

#ifndef __ASSEMBLY__

#include <linux/devfs_fs_kernel.h>
#include <asm/sn/vector.h>
#include <asm/sn/slotnum.h>
#include <asm/sn/arch.h>

typedef uint64_t	router_reg_t;

#define MAX_ROUTERS	64

#define MAX_ROUTER_PATH	80

#define ROUTER_REG_CAST		(volatile router_reg_t *)
#define PS_UINT_CAST		(__psunsigned_t)
#define UINT64_CAST		(uint64_t)
typedef signed char port_no_t;	 /* Type for router port number      */

#else 

#define ROUTERREG_CAST
#define PS_UINT_CAST
#define UINT64_CAST

#endif /* __ASSEMBLY__ */

#define MAX_ROUTER_PORTS (8)	 /* Max. number of ports on a router */

#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1)	/* for 0 based references */

#define PORT_INVALID (-1)	 /* Invalid port number              */

#define	IS_META(_rp)	((_rp)->flags & PCFG_ROUTER_META)

#define	IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)

/*
 * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
 * port to generate an output port.
 *
 * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
 * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
 *
 * These are written to work on unsigned data.
 */

#define RR_TURN(_L, count)	((_L) + (count) > MAX_ROUTER_PORTS ?	\
				 (_L) + (count) - MAX_ROUTER_PORTS :	\
				 (_L) + (count))

#define RR_DISTANCE(_LS, _LD)	((_LD) >= (_LS) ?			\
				 (_LD) - (_LS) :			\
				 (_LD) + MAX_ROUTER_PORTS - (_LS))

/* Router register addresses */

#define RR_STATUS_REV_ID	0x00000	/* Status register and Revision ID  */
#define RR_PORT_RESET		0x00008	/* Multiple port reset              */
#define RR_PROT_CONF		0x00010	/* Inter-partition protection conf. */
#define RR_GLOBAL_PORT_DEF	0x00018 /* Global Port definitions          */
#define RR_GLOBAL_PARMS0	0x00020	/* Parameters shared by all 8 ports */
#define RR_GLOBAL_PARMS1	0x00028	/* Parameters shared by all 8 ports */
#define RR_DIAG_PARMS		0x00030	/* Parameters for diag. testing     */
#define RR_DEBUG_ADDR		0x00038 /* Debug address select - debug port*/
#define RR_LB_TO_L2		0x00040 /* Local Block to L2 cntrl intf reg */ 
#define RR_L2_TO_LB		0x00048 /* L2 cntrl intf to Local Block reg */
#define RR_JBUS_CONTROL		0x00050 /* read/write timing for JBUS intf  */

#define RR_SCRATCH_REG0		0x00100	/* Scratch 0 is 64 bits */
#define RR_SCRATCH_REG1		0x00108	/* Scratch 1 is 64 bits */
#define RR_SCRATCH_REG2		0x00110	/* Scratch 2 is 64 bits */
#define RR_SCRATCH_REG3		0x00118	/* Scratch 3 is 1 bit */
#define RR_SCRATCH_REG4		0x00120	/* Scratch 4 is 1 bit */

#define RR_JBUS0(_D)		(((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses   */
#define RR_JBUS1(_D)		(((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses   */

#define RR_SCRATCH_REG0_WZ	0x00500	/* Scratch 0 is 64 bits */
#define RR_SCRATCH_REG1_WZ	0x00508	/* Scratch 1 is 64 bits */
#define RR_SCRATCH_REG2_WZ	0x00510	/* Scratch 2 is 64 bits */
#define RR_SCRATCH_REG3_SZ	0x00518	/* Scratch 3 is 1 bit */
#define RR_SCRATCH_REG4_SZ	0x00520	/* Scratch 4 is 1 bit */

#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
/* Port-specific registers (_L is the link number from 1 to 8) */

#define RR_PORT_PARMS(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters     */
#define RR_STATUS_ERROR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs  */
#define RR_CHANNEL_TEST(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
#define RR_RESET_MASK(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask  */
#define RR_HISTOGRAM0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
#define RR_HISTOGRAM1(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
#define RR_HISTOGRAM0_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
#define RR_HISTOGRAM1_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
#define RR_ERROR_CLEAR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors  */
#define RR_GLOBAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
#define RR_LOCAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))

#define RR_META_ENTRIES		16

#define RR_LOCAL_ENTRIES	128

/*
 * RR_STATUS_REV_ID mask and shift definitions
 */

#define RSRI_INPORT_SHFT	52
#define RSRI_INPORT_MASK	(UINT64_CAST 0xf << 52)
#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
#define RSRI_LINKWORKING(_L)	(UINT64_CAST 1 << (35 + 2 * (_L)))
#define RSRI_LINKRESETFAIL(_L)	(UINT64_CAST 1 << (34 + 2 * (_L)))
#define RSRI_LSTAT_SHFT(_L)	(34 + 2 * (_L))
#define RSRI_LSTAT_MASK(_L)	(UINT64_CAST 0x3 << 34 + 2 * (_L))
#define RSRI_LOCALSBERROR	(UINT64_CAST 1 << 35)
#define RSRI_LOCALSTUCK		(UINT64_CAST 1 << 34)
#define RSRI_LOCALBADVEC	(UINT64_CAST 1 << 33)
#define RSRI_LOCALTAILERR	(UINT64_CAST 1 << 32)
#define RSRI_LOCAL_SHFT 	32
#define RSRI_LOCAL_MASK		(UINT64_CAST 0xf << 32)
#define RSRI_CHIPREV_SHFT	28
#define RSRI_CHIPREV_MASK	(UINT64_CAST 0xf << 28)
#define RSRI_CHIPID_SHFT	12
#define RSRI_CHIPID_MASK	(UINT64_CAST 0xffff << 12)
#define RSRI_MFGID_SHFT		1
#define RSRI_MFGID_MASK		(UINT64_CAST 0x7ff << 1)

#define RSRI_LSTAT_WENTDOWN	0
#define RSRI_LSTAT_RESETFAIL	1
#define RSRI_LSTAT_LINKUP	2
#define RSRI_LSTAT_NOTUSED	3

/*
 * RR_PORT_RESET mask definitions
 */

#define RPRESET_WARM		(UINT64_CAST 1 << 9)
#define RPRESET_LINK(_L)	(UINT64_CAST 1 << (_L))
#define RPRESET_LOCAL		(UINT64_CAST 1)

/*
 * RR_PROT_CONF mask and shift definitions
 */

#define RPCONF_DIRCMPDIS_SHFT	13
#define RPCONF_DIRCMPDIS_MASK	(UINT64_CAST 1 << 13)
#define RPCONF_FORCELOCAL	(UINT64_CAST 1 << 12)
#define RPCONF_FLOCAL_SHFT	12
#define RPCONF_METAID_SHFT	8
#define RPCONF_METAID_MASK	(UINT64_CAST 0xf << 8)
#define RPCONF_RESETOK(_L)	(UINT64_CAST 1 << ((_L) - 1))

/*
 * RR_GLOBAL_PORT_DEF mask and shift definitions
 */

#define RGPD_MGLBLNHBR_ID_SHFT	12	/* -global neighbor ID */
#define RGPD_MGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 12)
#define RGPD_MGLBLNHBR_VLD_SHFT	11	/* -global neighbor Valid */
#define RGPD_MGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 11)
#define RGPD_MGLBLPORT_SHFT	8	/* -global neighbor Port */
#define RGPD_MGLBLPORT_MASK	(UINT64_CAST 0x7 << 8)
#define RGPD_PGLBLNHBR_ID_SHFT	4	/* +global neighbor ID */
#define RGPD_PGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 4)
#define RGPD_PGLBLNHBR_VLD_SHFT	3	/* +global neighbor Valid */
#define RGPD_PGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 3)
#define RGPD_PGLBLPORT_SHFT	0	/* +global neighbor Port */
#define RGPD_PGLBLPORT_MASK	(UINT64_CAST 0x7 << 0)

#define GLBL_PARMS_REGS		2	/* Two Global Parms registers */

/*
 * RR_GLOBAL_PARMS0 mask and shift definitions
 */

#define RGPARM0_ARB_VALUE_SHFT	54	/* Local Block Arbitration State */
#define RGPARM0_ARB_VALUE_MASK	(UINT64_CAST 0x7 << 54)
#define RGPARM0_ROTATEARB_SHFT	53	/* Rotate Local Block Arbitration */
#define RGPARM0_ROTATEARB_MASK	(UINT64_CAST 0x1 << 53)
#define RGPARM0_FAIREN_SHFT	52	/* Fairness logic Enable */
#define RGPARM0_FAIREN_MASK	(UINT64_CAST 0x1 << 52)
#define RGPARM0_LOCGNTTO_SHFT	40	/* Local grant timeout */
#define RGPARM0_LOCGNTTO_MASK	(UINT64_CAST 0xfff << 40)
#define RGPARM0_DATELINE_SHFT	38	/* Dateline crossing router */
#define RGPARM0_DATELINE_MASK	(UINT64_CAST 0x1 << 38)
#define RGPARM0_MAXRETRY_SHFT	28	/* Max retry count */
#define RGPARM0_MAXRETRY_MASK	(UINT64_CAST 0x3ff << 28)
#define RGPARM0_URGWRAP_SHFT	20	/* Urgent wrap */
#define RGPARM0_URGWRAP_MASK	(UINT64_CAST 0xff << 20)
#define RGPARM0_DEADLKTO_SHFT	16	/* Deadlock timeout */
#define RGPARM0_DEADLKTO_MASK	(UINT64_CAST 0xf << 16)
#define RGPARM0_URGVAL_SHFT	12	/* Urgent value */
#define RGPARM0_URGVAL_MASK	(UINT64_CAST 0xf << 12)
#define RGPARM0_VCHSELEN_SHFT	11	/* VCH_SEL_EN */
#define RGPARM0_VCHSELEN_MASK	(UINT64_CAST 0x1 << 11)
#define RGPARM0_LOCURGTO_SHFT	9	/* Local urgent timeout */
#define RGPARM0_LOCURGTO_MASK	(UINT64_CAST 0x3 << 9)
#define RGPARM0_TAILVAL_SHFT	5	/* Tail value */
#define RGPARM0_TAILVAL_MASK	(UINT64_CAST 0xf << 5)
#define RGPARM0_CLOCK_SHFT	1	/* Global clock select */
#define RGPARM0_CLOCK_MASK	(UINT64_CAST 0xf << 1)
#define RGPARM0_BYPEN_SHFT	0
#define RGPARM0_BYPEN_MASK	(UINT64_CAST 1)	/* Bypass enable */

/*
 * RR_GLOBAL_PARMS1 shift and mask definitions
 */

#define RGPARM1_TTOWRAP_SHFT	12	/* Tail timeout wrap */
#define RGPARM1_TTOWRAP_MASK	(UINT64_CAST 0xfffff << 12)
#define RGPARM1_AGERATE_SHFT	8	/* Age rate */
#define RGPARM1_AGERATE_MASK	(UINT64_CAST 0xf << 8)
#define RGPARM1_JSWSTAT_SHFT	0	/* JTAG Sw Register bits */
#define RGPARM1_JSWSTAT_MASK	(UINT64_CAST 0xff << 0)

/*
 * RR_DIAG_PARMS mask and shift definitions
 */

#define RDPARM_ABSHISTOGRAM	(UINT64_CAST 1 << 17)	/* Absolute histgrm */
#define RDPARM_DEADLOCKRESET	(UINT64_CAST 1 << 16)	/* Reset on deadlck */
#define RDPARM_DISABLE(_L)	(UINT64_CAST 1 << ((_L) +  7))
#define RDPARM_SENDERROR(_L)	(UINT64_CAST 1 << ((_L) -  1))

/*
 * RR_DEBUG_ADDR mask and shift definitions
 */

#define RDA_DATA_SHFT		10	/* Observed debug data */
#define RDA_DATA_MASK		(UINT64_CAST 0xffff << 10)
#define RDA_ADDR_SHFT		0	/* debug address for data */
#define RDA_ADDR_MASK		(UINT64_CAST 0x3ff << 0)

/*
 * RR_LB_TO_L2 mask and shift definitions
 */

#define RLBTOL2_DATA_VLD_SHFT	32	/* data is valid for JTAG controller */
#define RLBTOL2_DATA_VLD_MASK	(UINT64_CAST 0x1 << 32)
#define RLBTOL2_DATA_SHFT	0	/* data bits for JTAG controller */
#define RLBTOL2_DATA_MASK	(UINT64_CAST 0xffffffff)

/*
 * RR_L2_TO_LB mask and shift definitions
 */

#define RL2TOLB_DATA_VLD_SHFT	33	/* data is valid from JTAG controller */
#define RL2TOLB_DATA_VLD_MASK	(UINT64_CAST 0x1 << 33)
#define RL2TOLB_PARITY_SHFT	32	/* sw implemented parity for data */
#define RL2TOLB_PARITY_MASK	(UINT64_CAST 0x1 << 32)
#define RL2TOLB_DATA_SHFT	0	/* data bits from JTAG controller */
#define RL2TOLB_DATA_MASK	(UINT64_CAST 0xffffffff)

/*
 * RR_JBUS_CONTROL mask and shift definitions
 */

#define RJC_POS_BITS_SHFT	20	/* Router position bits */
#define RJC_POS_BITS_MASK	(UINT64_CAST 0xf << 20)
#define RJC_RD_DATA_STROBE_SHFT	16	/* count when read data is strobed in */
#define RJC_RD_DATA_STROBE_MASK	(UINT64_CAST 0xf << 16)
#define RJC_WE_OE_HOLD_SHFT	8	/* time OE or WE is held */
#define RJC_WE_OE_HOLD_MASK	(UINT64_CAST 0xff << 8)
#define RJC_ADDR_SET_HLD_SHFT	0	/* time address driven around OE/WE */
#define RJC_ADDR_SET_HLD_MASK	(UINT64_CAST 0xff)

/*
 * RR_SCRATCH_REGx mask and shift definitions
 *  note: these fields represent a software convention, and are not
 *        understood/interpreted by the hardware. 
 */

#define	RSCR0_BOOTED_SHFT	63
#define	RSCR0_BOOTED_MASK	(UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT)
#define RSCR0_LOCALID_SHFT	56
#define RSCR0_LOCALID_MASK	(UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT)
#define	RSCR0_UNUSED_SHFT	48
#define	RSCR0_UNUSED_MASK	(UINT64_CAST 0xff << RSCR0_UNUSED_SHFT)
#define RSCR0_NIC_SHFT		0
#define RSCR0_NIC_MASK		(UINT64_CAST 0xffffffffffff)

#define RSCR1_MODID_SHFT	0
#define RSCR1_MODID_MASK	(UINT64_CAST 0xffff)

/*
 * RR_VECTOR_HW_BAR mask and shift definitions
 */

#define BAR_TX_SHFT		27	/* Barrier in trans(m)it when read */
#define BAR_TX_MASK		(UINT64_CAST 1 << BAR_TX_SHFT)
#define BAR_VLD_SHFT		26	/* Valid Configuration */
#define BAR_VLD_MASK		(UINT64_CAST 1 << BAR_VLD_SHFT)
#define BAR_SEQ_SHFT		24	/* Sequence number */
#define BAR_SEQ_MASK		(UINT64_CAST 3 << BAR_SEQ_SHFT)
#define BAR_LEAFSTATE_SHFT	18	/* Leaf State */
#define BAR_LEAFSTATE_MASK	(UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT)
#define BAR_PARENT_SHFT		14	/* Parent Port */
#define BAR_PARENT_MASK		(UINT64_CAST 0xf << BAR_PARENT_SHFT)
#define BAR_CHILDREN_SHFT	6	/* Child Select port bits */
#define BAR_CHILDREN_MASK	(UINT64_CAST 0xff << BAR_CHILDREN_SHFT)
#define BAR_LEAFCOUNT_SHFT	0	/* Leaf Count to trigger parent */
#define BAR_LEAFCOUNT_MASK	(UINT64_CAST 0x3f)

/*
 * RR_PORT_PARMS(_L) mask and shift definitions
 */

#define RPPARM_MIPRESETEN_SHFT	29	/* Message In Progress reset enable */
#define RPPARM_MIPRESETEN_MASK	(UINT64_CAST 0x1 << 29)
#define RPPARM_UBAREN_SHFT	28	/* Enable user barrier requests */
#define RPPARM_UBAREN_MASK	(UINT64_CAST 0x1 << 28)
#define RPPARM_OUTPDTO_SHFT	24	/* Output Port Deadlock TO value */
#define RPPARM_OUTPDTO_MASK	(UINT64_CAST 0xf << 24)