ioc3.h

linux-2.4.29操作系统的源码

/*
 * Copyright (c) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
 * 
 * This program is free software; you can redistribute it and/or modify it 
 * under the terms of version 2 of the GNU General Public License 
 * as published by the Free Software Foundation.
 * 
 * This program is distributed in the hope that it would be useful, but 
 * WITHOUT ANY WARRANTY; without even the implied warranty of 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
 * 
 * Further, this software is distributed without any warranty that it is 
 * free of the rightful claim of any third person regarding infringement 
 * or the like.  Any license provided herein, whether implied or 
 * otherwise, applies only to this software file.  Patent licenses, if 
 * any, provided herein do not apply to combinations of this program with 
 * other software, or any other product whatsoever.
 * 
 * You should have received a copy of the GNU General Public 
 * License along with this program; if not, write the Free Software 
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 * 
 * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
 * Mountain View, CA  94043, or:
 * 
 * http://www.sgi.com 
 * 
 * For further information regarding this notice, see: 
 * 
 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
 */

/* $Id: ioc3.h,v 1.2 2000/11/16 19:49:17 pfg Exp $
 *
 * Copyright (C) 1999 Ralf Baechle
 * This file is part of the Linux driver for the SGI IOC3.
 */
#ifndef _ASM_IA64_SN_IOC3_H
#define _ASM_IA64_SN_IOC3_H

#include <asm/types.h>

/* SUPERIO uart register map */
typedef volatile struct ioc3_uartregs {
	union {
		volatile u8	rbr;	/* read only, DLAB == 0 */
		volatile u8	thr;	/* write only, DLAB == 0 */
		volatile u8	dll;	/* DLAB == 1 */
	} u1;
	union {
		volatile u8	ier;	/* DLAB == 0 */
		volatile u8	dlm;	/* DLAB == 1 */
	} u2;
	union {
		volatile u8	iir;	/* read only */
		volatile u8	fcr;	/* write only */
	} u3;
	volatile u8	    iu_lcr;
	volatile u8	    iu_mcr;
	volatile u8	    iu_lsr;
	volatile u8	    iu_msr;
	volatile u8	    iu_scr;
} ioc3_uregs_t;

#define iu_rbr u1.rbr
#define iu_thr u1.thr
#define iu_dll u1.dll
#define iu_ier u2.ier
#define iu_dlm u2.dlm
#define iu_iir u3.iir
#define iu_fcr u3.fcr

struct ioc3_sioregs {
	volatile u8		fill[0x141];	/* starts at 0x141 */

	volatile u8		uartc;
	volatile u8		kbdcg;

	volatile u8		fill0[0x150 - 0x142 - 1];

	volatile u8		pp_data;
	volatile u8		pp_dsr;
	volatile u8		pp_dcr;

	volatile u8		fill1[0x158 - 0x152 - 1];

	volatile u8		pp_fifa;
	volatile u8		pp_cfgb;
	volatile u8		pp_ecr;

	volatile u8		fill2[0x168 - 0x15a - 1];

	volatile u8		rtcad;
	volatile u8		rtcdat;

	volatile u8		fill3[0x170 - 0x169 - 1];

	struct ioc3_uartregs    uartb;	/* 0x20170  */
	struct ioc3_uartregs    uarta;	/* 0x20178  */
};

/* Register layout of IOC3 in configuration space.  */
struct ioc3 {
	volatile u32	pad0[7];	/* 0x00000  */
	volatile u32	sio_ir;		/* 0x0001c  */
	volatile u32	sio_ies;	/* 0x00020  */
	volatile u32	sio_iec;	/* 0x00024  */
	volatile u32	sio_cr;		/* 0x00028  */
	volatile u32	int_out;	/* 0x0002c  */
	volatile u32	mcr;		/* 0x00030  */

	/* General Purpose I/O registers  */
	volatile u32	gpcr_s;		/* 0x00034  */
	volatile u32	gpcr_c;		/* 0x00038  */
	volatile u32	gpdr;		/* 0x0003c  */
	volatile u32	gppr_0;		/* 0x00040  */
	volatile u32	gppr_1;		/* 0x00044  */
	volatile u32	gppr_2;		/* 0x00048  */
	volatile u32	gppr_3;		/* 0x0004c  */
	volatile u32	gppr_4;		/* 0x00050  */
	volatile u32	gppr_5;		/* 0x00054  */
	volatile u32	gppr_6;		/* 0x00058  */
	volatile u32	gppr_7;		/* 0x0005c  */
	volatile u32	gppr_8;		/* 0x00060  */
	volatile u32	gppr_9;		/* 0x00064  */
	volatile u32	gppr_10;	/* 0x00068  */
	volatile u32	gppr_11;	/* 0x0006c  */
	volatile u32	gppr_12;	/* 0x00070  */
	volatile u32	gppr_13;	/* 0x00074  */
	volatile u32	gppr_14;	/* 0x00078  */
	volatile u32	gppr_15;	/* 0x0007c  */

	/* Parallel Port Registers  */
	volatile u32	ppbr_h_a;	/* 0x00080  */
	volatile u32	ppbr_l_a;	/* 0x00084  */
	volatile u32	ppcr_a;		/* 0x00088  */
	volatile u32	ppcr;		/* 0x0008c  */
	volatile u32	ppbr_h_b;	/* 0x00090  */
	volatile u32	ppbr_l_b;	/* 0x00094  */
	volatile u32	ppcr_b;		/* 0x00098  */

	/* Keyboard and Mouse Registers  */
	volatile u32	km_csr;		/* 0x0009c  */
	volatile u32	k_rd;		/* 0x000a0  */
	volatile u32	m_rd;		/* 0x000a4  */
	volatile u32	k_wd;		/* 0x000a8  */
	volatile u32	m_wd;		/* 0x000ac  */

	/* Serial Port Registers  */
	volatile u32	sbbr_h;		/* 0x000b0  */
	volatile u32	sbbr_l;		/* 0x000b4  */
	volatile u32	sscr_a;		/* 0x000b8  */
	volatile u32	stpir_a;	/* 0x000bc  */
	volatile u32	stcir_a;	/* 0x000c0  */
	volatile u32	srpir_a;	/* 0x000c4  */
	volatile u32	srcir_a;	/* 0x000c8  */
	volatile u32	srtr_a;		/* 0x000cc  */
	volatile u32	shadow_a;	/* 0x000d0  */
	volatile u32	sscr_b;		/* 0x000d4  */
	volatile u32	stpir_b;	/* 0x000d8  */
	volatile u32	stcir_b;	/* 0x000dc  */
	volatile u32	srpir_b;	/* 0x000e0  */
	volatile u32	srcir_b;	/* 0x000e4  */
	volatile u32	srtr_b;		/* 0x000e8  */
	volatile u32	shadow_b;	/* 0x000ec  */

	/* Ethernet Registers  */
	volatile u32	emcr;		/* 0x000f0  */
	volatile u32	eisr;		/* 0x000f4  */
	volatile u32	eier;		/* 0x000f8  */
	volatile u32	ercsr;		/* 0x000fc  */
	volatile u32	erbr_h;		/* 0x00100  */
	volatile u32	erbr_l;		/* 0x00104  */
	volatile u32	erbar;		/* 0x00108  */
	volatile u32	ercir;		/* 0x0010c  */
	volatile u32	erpir;		/* 0x00110  */
	volatile u32	ertr;		/* 0x00114  */
	volatile u32	etcsr;		/* 0x00118  */
	volatile u32	ersr;		/* 0x0011c  */
	volatile u32	etcdc;		/* 0x00120  */
	volatile u32	ebir;		/* 0x00124  */
	volatile u32	etbr_h;		/* 0x00128  */
	volatile u32	etbr_l;		/* 0x0012c  */
	volatile u32	etcir;		/* 0x00130  */
	volatile u32	etpir;		/* 0x00134  */
	volatile u32	emar_h;		/* 0x00138  */
	volatile u32	emar_l;		/* 0x0013c  */
	volatile u32	ehar_h;		/* 0x00140  */
	volatile u32	ehar_l;		/* 0x00144  */
	volatile u32	micr;		/* 0x00148  */
	volatile u32	midr_r;		/* 0x0014c  */
	volatile u32    midr_w;           /* 0x00150  */
	volatile u32	pad1[(0x20000 - 0x00154) / 4];

	/* SuperIO Registers  XXX */
	struct ioc3_sioregs	sregs;	/* 0x20000 */
	volatile u32	pad2[(0x40000 - 0x20180) / 4];

	/* SSRAM Diagnostic Access */
	volatile u32	ssram[(0x80000 - 0x40000) / 4];

	/* Bytebus device offsets
	   0x80000 -   Access to the generic devices selected with   DEV0
	   0x9FFFF     bytebus DEV_SEL_0
	   0xA0000 -   Access to the generic devices selected with   DEV1
	   0xBFFFF     bytebus DEV_SEL_1
	   0xC0000 -   Access to the generic devices selected with   DEV2
	   0xDFFFF     bytebus DEV_SEL_2
	   0xE0000 -   Access to the generic devices selected with   DEV3
	   0xFFFFF     bytebus DEV_SEL_3  */
};

/*
 * Ethernet RX Buffer
 */
struct ioc3_erxbuf {
	u32	w0;			/* first word (valid,bcnt,cksum) */
	u32	err;			/* second word various errors */
	/* next comes n bytes of padding */
	/* then the received ethernet frame itself */
};

#define ERXBUF_IPCKSUM_MASK	0x0000ffff
#define ERXBUF_BYTECNT_MASK	0x07ff0000
#define ERXBUF_BYTECNT_SHIFT	16
#define ERXBUF_V		0x80000000

#define ERXBUF_CRCERR		0x00000001	/* aka RSV15 */
#define ERXBUF_FRAMERR		0x00000002	/* aka RSV14 */
#define ERXBUF_CODERR		0x00000004	/* aka RSV13 */
#define ERXBUF_INVPREAMB	0x00000008	/* aka RSV18 */
#define ERXBUF_LOLEN		0x00007000	/* aka RSV2_0 */
#define ERXBUF_HILEN		0x03ff0000	/* aka RSV12_3 */
#define ERXBUF_MULTICAST	0x04000000	/* aka RSV16 */
#define ERXBUF_BROADCAST	0x08000000	/* aka RSV17 */
#define ERXBUF_LONGEVENT	0x10000000	/* aka RSV19 */
#define ERXBUF_BADPKT		0x20000000	/* aka RSV20 */
#define ERXBUF_GOODPKT		0x40000000	/* aka RSV21 */
#define ERXBUF_CARRIER		0x80000000	/* aka RSV22 */

/*
 * Ethernet TX Descriptor
 */
#define ETXD_DATALEN    104
struct ioc3_etxd {
	u32	cmd;				/* command field */
	u32	bufcnt;				/* buffer counts field */
	u64	p1;				/* buffer pointer 1 */
	u64	p2;				/* buffer pointer 2 */
	u8	data[ETXD_DATALEN];		/* opt. tx data */
};

#define ETXD_BYTECNT_MASK	0x000007ff	/* total byte count */
#define ETXD_INTWHENDONE	0x00001000	/* intr when done */
#define ETXD_D0V		0x00010000	/* data 0 valid */
#define ETXD_B1V		0x00020000	/* buf 1 valid */
#define ETXD_B2V		0x00040000	/* buf 2 valid */
#define ETXD_DOCHECKSUM		0x00080000	/* insert ip cksum */
#define ETXD_CHKOFF_MASK	0x07f00000	/* cksum byte offset */
#define ETXD_CHKOFF_SHIFT	20

#define ETXD_D0CNT_MASK		0x0000007f
#define ETXD_B1CNT_MASK		0x0007ff00
#define ETXD_B1CNT_SHIFT	8
#define ETXD_B2CNT_MASK		0x7ff00000
#define ETXD_B2CNT_SHIFT	20

/*
 * Bytebus device space
 */
#define IOC3_BYTEBUS_DEV0	0x80000L
#define IOC3_BYTEBUS_DEV1	0xa0000L
#define IOC3_BYTEBUS_DEV2	0xc0000L
#define IOC3_BYTEBUS_DEV3	0xe0000L

/* ------------------------------------------------------------------------- */

/* Superio Registers (PIO Access) */
#define IOC3_SIO_BASE		0x20000
#define IOC3_SIO_UARTC		(IOC3_SIO_BASE+0x141)	/* UART Config */
#define IOC3_SIO_KBDCG		(IOC3_SIO_BASE+0x142)	/* KBD Config */
#define IOC3_SIO_PP_BASE	(IOC3_SIO_BASE+PP_BASE)		/* Parallel Port */
#define IOC3_SIO_RTC_BASE	(IOC3_SIO_BASE+0x168)	/* Real Time Clock */
#define IOC3_SIO_UB_BASE	(IOC3_SIO_BASE+UARTB_BASE)	/* UART B */
#define IOC3_SIO_UA_BASE	(IOC3_SIO_BASE+UARTA_BASE)	/* UART A */

/* SSRAM Diagnostic Access */
#define IOC3_SSRAM	IOC3_RAM_OFF	/* base of SSRAM diagnostic access */
#define IOC3_SSRAM_LEN	0x40000 /* 256kb (address space size, may not be fully populated) */
#define IOC3_SSRAM_DM	0x0000ffff	/* data mask */
#define IOC3_SSRAM_PM	0x00010000	/* parity mask */

/* bitmasks for PCI_SCR */
#define PCI_SCR_PAR_RESP_EN	0x00000040	/* enb PCI parity checking */
#define PCI_SCR_SERR_EN		0x00000100	/* enable the SERR# driver */
#define PCI_SCR_DROP_MODE_EN	0x00008000	/* drop pios on parity err */
#define PCI_SCR_RX_SERR		(0x1 << 16)
#define PCI_SCR_DROP_MODE	(0x1 << 17)
#define PCI_SCR_SIG_PAR_ERR	(0x1 << 24)
#define PCI_SCR_SIG_TAR_ABRT	(0x1 << 27)
#define PCI_SCR_RX_TAR_ABRT	(0x1 << 28)
#define PCI_SCR_SIG_MST_ABRT	(0x1 << 29)
#define PCI_SCR_SIG_SERR	(0x1 << 30)
#define PCI_SCR_PAR_ERR		(0x1 << 31)

/* bitmasks for IOC3_KM_CSR */
#define KM_CSR_K_WRT_PEND 0x00000001	/* kbd port xmitting or resetting */
#define KM_CSR_M_WRT_PEND 0x00000002	/* mouse port xmitting or resetting */
#define KM_CSR_K_LCB	  0x00000004	/* Line Cntrl Bit for last KBD write */
#define KM_CSR_M_LCB	  0x00000008	/* same for mouse */
#define KM_CSR_K_DATA	  0x00000010	/* state of kbd data line */
#define KM_CSR_K_CLK	  0x00000020	/* state of kbd clock line */
#define KM_CSR_K_PULL_DATA 0x00000040	/* pull kbd data line low */
#define KM_CSR_K_PULL_CLK 0x00000080	/* pull kbd clock line low */
#define KM_CSR_M_DATA	  0x00000100	/* state of ms data line */
#define KM_CSR_M_CLK	  0x00000200	/* state of ms clock line */
#define KM_CSR_M_PULL_DATA 0x00000400	/* pull ms data line low */
#define KM_CSR_M_PULL_CLK 0x00000800	/* pull ms clock line low */
#define KM_CSR_EMM_MODE	  0x00001000	/* emulation mode */
#define KM_CSR_SIM_MODE	  0x00002000	/* clock X8 */
#define KM_CSR_K_SM_IDLE  0x00004000	/* Keyboard is idle */
#define KM_CSR_M_SM_IDLE  0x00008000	/* Mouse is idle */
#define KM_CSR_K_TO	  0x00010000	/* Keyboard trying to send/receive */
#define KM_CSR_M_TO	  0x00020000	/* Mouse trying to send/receive */
#define KM_CSR_K_TO_EN	  0x00040000	/* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
					   SIO_IR to assert */
#define KM_CSR_M_TO_EN	  0x00080000	/* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
					   SIO_IR to assert */
#define KM_CSR_K_CLAMP_ONE	0x00100000	/* Pull K_CLK low after rec. one char */
#define KM_CSR_M_CLAMP_ONE	0x00200000	/* Pull M_CLK low after rec. one char */
#define KM_CSR_K_CLAMP_THREE	0x00400000	/* Pull K_CLK low after rec. three chars */
#define KM_CSR_M_CLAMP_THREE	0x00800000	/* Pull M_CLK low after rec. three char */

/* bitmasks for IOC3_K_RD and IOC3_M_RD */
#define KM_RD_DATA_2	0x000000ff	/* 3rd char recvd since last read */
#define KM_RD_DATA_2_SHIFT 0
#define KM_RD_DATA_1	0x0000ff00	/* 2nd char recvd since last read */
#define KM_RD_DATA_1_SHIFT 8
#define KM_RD_DATA_0	0x00ff0000	/* 1st char recvd since last read */
#define KM_RD_DATA_0_SHIFT 16
#define KM_RD_FRAME_ERR_2 0x01000000	/*  framing or parity error in byte 2 */
#define KM_RD_FRAME_ERR_1 0x02000000	/* same for byte 1 */
#define KM_RD_FRAME_ERR_0 0x04000000	/* same for byte 0 */

#define KM_RD_KBD_MSE	0x08000000	/* 0 if from kbd, 1 if from mouse */
#define KM_RD_OFLO	0x10000000	/* 4th char recvd before this read */
#define KM_RD_VALID_2	0x20000000	/* DATA_2 valid */
#define KM_RD_VALID_1	0x40000000	/* DATA_1 valid */
#define KM_RD_VALID_0	0x80000000	/* DATA_0 valid */
#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)

/* bitmasks for IOC3_K_WD & IOC3_M_WD */
#define KM_WD_WRT_DATA	0x000000ff	/* write to keyboard/mouse port */