📄 sb1250_scd.h
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/* ********************************************************************* * SB1250 Board Support Package * * SCD Constants and Macros File: sb1250_scd.h * * This module contains constants and macros useful for * manipulating the System Control and Debug module on the 1250. * * SB1250 specification level: User's manual 1/02/02 * * Author: Mitch Lichtenberg * ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */#ifndef _SB1250_SCD_H#define _SB1250_SCD_H#include "sb1250_defs.h"/* ********************************************************************* * System control/debug registers ********************************************************************* *//* * System Revision Register (Table 4-1) */#define M_SYS_RESERVED _SB_MAKEMASK(8,0)#define S_SYS_REVISION _SB_MAKE64(8)#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION)#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)#if SIBYTE_HDR_FEATURE_CHIP(1250)#define K_SYS_REVISION_BCM1250_PASS1 1#define K_SYS_REVISION_BCM1250_PASS2 3#define K_SYS_REVISION_BCM1250_A10 11#define K_SYS_REVISION_BCM1250_PASS2_2 16#define K_SYS_REVISION_BCM1250_B2 17#define K_SYS_REVISION_BCM1250_PASS3 32#define K_SYS_REVISION_BCM1250_C1 33/* XXX: discourage people from using these constants. */#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3#endif /* 1250 */#if SIBYTE_HDR_FEATURE_CHIP(112x)#define K_SYS_REVISION_BCM112x_A1 32#define K_SYS_REVISION_BCM112x_A2 33#endif /* 112x *//* XXX: discourage people from using these constants. */#define S_SYS_PART _SB_MAKE64(16)#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)/* XXX: discourage people from using these constants. */#define K_SYS_PART_SB1250 0x1250#define K_SYS_PART_BCM1120 0x1121#define K_SYS_PART_BCM1125 0x1123#define K_SYS_PART_BCM1125H 0x1124/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */#define S_SYS_SOC_TYPE _SB_MAKE64(16)#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE)#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE)#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE)#define K_SYS_SOC_TYPE_BCM1250 0x0#define K_SYS_SOC_TYPE_BCM1120 0x1#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */#define K_SYS_SOC_TYPE_BCM1125 0x3#define K_SYS_SOC_TYPE_BCM1125H 0x4#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. *//* * Calculate correct SOC type given a copy of system revision register. * * (For the assembler version, sysrev and dest may be the same register. * Also, it clobbers AT.) */#ifdef __ASSEMBLER__#define SYS_SOC_TYPE(dest, sysrev) \ .set push ; \ .set reorder ; \ dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ b 992f ; \991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \992: \ .set pop#else#define SYS_SOC_TYPE(sysrev) \ ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))#endif#define S_SYS_WID _SB_MAKE64(32)#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)/* System Manufacturing Register* Register: SCD_SYSTEM_MANUF*/ /* Wafer ID: bits 31:0 */#define S_SYS_WAFERID1_200 _SB_MAKE64(0)#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) #define S_SYS_BIN _SB_MAKE64(32)#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN)#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) /* Wafer ID: bits 39:36 */#define S_SYS_WAFERID2_200 _SB_MAKE64(36)#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200)#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) /* Wafer ID: bits 39:0 */#define S_SYS_WAFERID_300 _SB_MAKE64(0)#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300)#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300)#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) #define S_SYS_XPOS _SB_MAKE64(40)#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS)#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS)#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) #define S_SYS_YPOS _SB_MAKE64(46)#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) /* * System Config Register (Table 4-2) * Register: SCD_SYSTEM_CFG */#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)#define S_SYS_PLL_DIV _SB_MAKE64(7)#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV)#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV)#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)#define S_SYS_BOOT_MODE _SB_MAKE64(17)#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE)#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)#define K_SYS_BOOT_MODE_ROM32 0#define K_SYS_BOOT_MODE_ROM8 1#define K_SYS_BOOT_MODE_SMBUS_SMALL 2#define K_SYS_BOOT_MODE_SMBUS_BIG 3#define M_SYS_PCI_HOST _SB_MAKEMASK1(19)#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)#define S_SYS_CONFIG 26#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG)#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)/* The following bits are writeable by JTAG only. */#define M_SYS_CLKSTOP _SB_MAKEMASK1(32)#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)#define S_SYS_CLKCOUNT 34#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT)#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)#define S_SYS_PLL_IREF 43#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF)#define S_SYS_PLL_VCO 45#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO)#define S_SYS_PLL_VREG 47#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG)#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)#define M_SYS_SCD_RESET _SB_MAKEMASK1(53)/* End of bits writable by JTAG only. */#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)#define M_SYS_UNICPU0 _SB_MAKEMASK1(56)#define M_SYS_UNICPU1 _SB_MAKEMASK1(57)#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)#define M_SYS_EXT_RESET _SB_MAKEMASK1(59)#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)#define M_SYS_MISR_MODE _SB_MAKEMASK1(61)#define M_SYS_MISR_RESET _SB_MAKEMASK1(62)#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_SYS_SW_FLAG _SB_MAKEMASK1(63)#endif /* 1250 PASS2 || 112x PASS1 *//* * Mailbox Registers (Table 4-3) * Registers: SCD_MBOX_CPU_x */#define S_MBOX_INT_3 0#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3)#define S_MBOX_INT_2 16#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2)#define S_MBOX_INT_1 32#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1)#define S_MBOX_INT_0 48#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0)/* * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) * Registers: SCD_WDOG_INIT_CNT_x */#define V_SCD_WDOG_FREQ 1000000#define S_SCD_WDOG_INIT 0#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT)#define S_SCD_WDOG_CNT 0#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT)#define S_SCD_WDOG_ENABLE 0#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)#define S_SCD_WDOG_RESET_TYPE 2#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE)#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE)#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE)#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */⌨️ 快捷键说明
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