sb1250_regs.h

linux-2.4.29操作系统的源码

#define R_DUART_CLK_SEL             0x130
#define R_DUART_CMD                 0x150
#define R_DUART_RX_HOLD             0x160
#define R_DUART_TX_HOLD             0x170

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_DUART_FULL_CTL	    0x140
#define R_DUART_OPCR_X		    0x180
#define R_DUART_AUXCTL_X	    0x190
#endif /* 1250 PASS2 || 112x PASS1 */


/*
 * The IMR and ISR can't be addressed with A_DUART_CHANREG,
 * so use this macro instead.
 */

#define R_DUART_AUX_CTRL            0x310
#define R_DUART_ISR_A               0x320
#define R_DUART_IMR_A               0x330
#define R_DUART_ISR_B               0x340
#define R_DUART_IMR_B               0x350
#define R_DUART_OUT_PORT            0x360
#define R_DUART_OPCR                0x370

#define R_DUART_SET_OPR		    0x3B0
#define R_DUART_CLEAR_OPR	    0x3C0

#define DUART_IMRISR_SPACING        0x20

#define R_DUART_IMRREG(chan)	    (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
#define R_DUART_ISRREG(chan)	    (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)

#define A_DUART_IMRREG(chan)	    (A_DUART + R_DUART_IMRREG(chan))
#define A_DUART_ISRREG(chan)	    (A_DUART + R_DUART_ISRREG(chan))




/*
 * These constants are the absolute addresses.
 */

#define A_DUART_MODE_REG_1_A        0x0010060100
#define A_DUART_MODE_REG_2_A        0x0010060110
#define A_DUART_STATUS_A            0x0010060120
#define A_DUART_CLK_SEL_A           0x0010060130
#define A_DUART_CMD_A               0x0010060150
#define A_DUART_RX_HOLD_A           0x0010060160
#define A_DUART_TX_HOLD_A           0x0010060170

#define A_DUART_MODE_REG_1_B        0x0010060200
#define A_DUART_MODE_REG_2_B        0x0010060210
#define A_DUART_STATUS_B            0x0010060220
#define A_DUART_CLK_SEL_B           0x0010060230
#define A_DUART_CMD_B               0x0010060250
#define A_DUART_RX_HOLD_B           0x0010060260
#define A_DUART_TX_HOLD_B           0x0010060270

#define A_DUART_INPORT_CHNG         0x0010060300
#define A_DUART_AUX_CTRL            0x0010060310
#define A_DUART_ISR_A               0x0010060320
#define A_DUART_IMR_A               0x0010060330
#define A_DUART_ISR_B               0x0010060340
#define A_DUART_IMR_B               0x0010060350
#define A_DUART_OUT_PORT            0x0010060360
#define A_DUART_OPCR                0x0010060370
#define A_DUART_IN_PORT             0x0010060380
#define A_DUART_ISR                 0x0010060390
#define A_DUART_IMR                 0x00100603A0
#define A_DUART_SET_OPR             0x00100603B0
#define A_DUART_CLEAR_OPR           0x00100603C0
#define A_DUART_INPORT_CHNG_A       0x00100603D0
#define A_DUART_INPORT_CHNG_B       0x00100603E0

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DUART_FULL_CTL_A	    0x0010060140
#define A_DUART_FULL_CTL_B	    0x0010060240

#define A_DUART_OPCR_A	  	    0x0010060180
#define A_DUART_OPCR_B	  	    0x0010060280

#define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
#endif /* 1250 PASS2 || 112x PASS1 */


/*  ********************************************************************* 
    * Synchronous Serial Registers
    ********************************************************************* */


#define A_SER_BASE_0                0x0010060400
#define A_SER_BASE_1                0x0010060800
#define SER_SPACING                 0x400

#define SER_DMA_TXRX_SPACING        0x80

#define SER_NUM_PORTS               2

#define A_SER_CHANNEL_BASE(sernum)                  \
            (A_SER_BASE_0 +                         \
             SER_SPACING*(sernum))

#define A_SER_REGISTER(sernum,reg)                  \
            (A_SER_BASE_0 +                         \
             SER_SPACING*(sernum) + (reg))


#define R_SER_DMA_CHANNELS		0   /* Relative to A_SER_BASE_x */

#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
             ((A_SER_CHANNEL_BASE(sernum)) +        \
             R_SER_DMA_CHANNELS +                   \
             (SER_DMA_TXRX_SPACING*(txrx)))

#define A_SER_DMA_REGISTER(sernum,txrx,reg)           \
            (A_SER_DMA_CHANNEL_BASE(sernum,txrx) +    \
            (reg))


/* 
 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
 */

#define R_SER_DMA_CONFIG0           0x00000000
#define R_SER_DMA_CONFIG1           0x00000008
#define R_SER_DMA_DSCR_BASE         0x00000010
#define R_SER_DMA_DSCR_CNT          0x00000018
#define R_SER_DMA_CUR_DSCRA         0x00000020
#define R_SER_DMA_CUR_DSCRB         0x00000028
#define R_SER_DMA_CUR_DSCRADDR      0x00000030

#define R_SER_DMA_CONFIG0_RX        0x00000000
#define R_SER_DMA_CONFIG1_RX        0x00000008
#define R_SER_DMA_DSCR_BASE_RX      0x00000010
#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
#define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030

#define R_SER_DMA_CONFIG0_TX        0x00000080
#define R_SER_DMA_CONFIG1_TX        0x00000088
#define R_SER_DMA_DSCR_BASE_TX      0x00000090
#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
#define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0

#define R_SER_MODE                  0x00000100
#define R_SER_MINFRM_SZ             0x00000108
#define R_SER_MAXFRM_SZ             0x00000110
#define R_SER_ADDR                  0x00000118
#define R_SER_USR0_ADDR             0x00000120
#define R_SER_USR1_ADDR             0x00000128
#define R_SER_USR2_ADDR             0x00000130
#define R_SER_USR3_ADDR             0x00000138
#define R_SER_CMD                   0x00000140
#define R_SER_TX_RD_THRSH           0x00000160
#define R_SER_TX_WR_THRSH           0x00000168
#define R_SER_RX_RD_THRSH           0x00000170
#define R_SER_LINE_MODE		    0x00000178
#define R_SER_DMA_ENABLE            0x00000180
#define R_SER_INT_MASK              0x00000190
#define R_SER_STATUS                0x00000188
#define R_SER_STATUS_DEBUG          0x000001A8
#define R_SER_RX_TABLE_BASE         0x00000200
#define SER_RX_TABLE_COUNT          16
#define R_SER_TX_TABLE_BASE         0x00000300
#define SER_TX_TABLE_COUNT          16

/* RMON Counters */
#define R_SER_RMON_TX_BYTE_LO       0x000001C0
#define R_SER_RMON_TX_BYTE_HI       0x000001C8
#define R_SER_RMON_RX_BYTE_LO       0x000001D0
#define R_SER_RMON_RX_BYTE_HI       0x000001D8
#define R_SER_RMON_TX_UNDERRUN      0x000001E0
#define R_SER_RMON_RX_OVERFLOW      0x000001E8
#define R_SER_RMON_RX_ERRORS        0x000001F0
#define R_SER_RMON_RX_BADADDR       0x000001F8

/*  ********************************************************************* 
    * Generic Bus Registers
    ********************************************************************* */

#define IO_EXT_CFG_COUNT            8

#define A_IO_EXT_BASE		    0x0010061000
#define A_IO_EXT_REG(r)		    (A_IO_EXT_BASE + (r))

#define A_IO_EXT_CFG_BASE           0x0010061000
#define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
#define A_IO_EXT_START_ADDR_BASE    0x0010061200
#define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
#define A_IO_EXT_TIME_CFG1_BASE     0x0010061700

#define IO_EXT_REGISTER_SPACING	    8
#define A_IO_EXT_CS_BASE(cs)	    (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
#define R_IO_EXT_REG(reg,cs)	    ((cs)*IO_EXT_REGISTER_SPACING + (reg))

#define R_IO_EXT_CFG		    0x0000
#define R_IO_EXT_MULT_SIZE          0x0100
#define R_IO_EXT_START_ADDR	    0x0200
#define R_IO_EXT_TIME_CFG0          0x0600
#define R_IO_EXT_TIME_CFG1          0x0700


#define A_IO_INTERRUPT_STATUS       0x0010061A00
#define A_IO_INTERRUPT_DATA0        0x0010061A10
#define A_IO_INTERRUPT_DATA1        0x0010061A18
#define A_IO_INTERRUPT_DATA2        0x0010061A20
#define A_IO_INTERRUPT_DATA3        0x0010061A28
#define A_IO_INTERRUPT_ADDR0        0x0010061A30
#define A_IO_INTERRUPT_ADDR1        0x0010061A40
#define A_IO_INTERRUPT_PARITY       0x0010061A50
#define A_IO_PCMCIA_CFG             0x0010061A60
#define A_IO_PCMCIA_STATUS          0x0010061A70
#define A_IO_DRIVE_0		    0x0010061300
#define A_IO_DRIVE_1		    0x0010061308
#define A_IO_DRIVE_2		    0x0010061310
#define A_IO_DRIVE_3		    0x0010061318
#define A_IO_DRIVE_BASE		    A_IO_DRIVE_0
#define IO_DRIVE_REGISTER_SPACING   8
#define R_IO_DRIVE(x)		    ((x)*IO_DRIVE_REGISTER_SPACING)
#define A_IO_DRIVE(x)		    (A_IO_DRIVE_BASE + R_IO_DRIVE(x))

#define R_IO_INTERRUPT_STATUS       0x0A00
#define R_IO_INTERRUPT_DATA0        0x0A10
#define R_IO_INTERRUPT_DATA1        0x0A18
#define R_IO_INTERRUPT_DATA2        0x0A20
#define R_IO_INTERRUPT_DATA3        0x0A28
#define R_IO_INTERRUPT_ADDR0        0x0A30
#define R_IO_INTERRUPT_ADDR1        0x0A40
#define R_IO_INTERRUPT_PARITY       0x0A50
#define R_IO_PCMCIA_CFG             0x0A60
#define R_IO_PCMCIA_STATUS          0x0A70

/*  ********************************************************************* 
    * GPIO Registers
    ********************************************************************* */

#define A_GPIO_CLR_EDGE             0x0010061A80
#define A_GPIO_INT_TYPE             0x0010061A88
#define A_GPIO_INPUT_INVERT         0x0010061A90
#define A_GPIO_GLITCH               0x0010061A98
#define A_GPIO_READ                 0x0010061AA0
#define A_GPIO_DIRECTION            0x0010061AA8
#define A_GPIO_PIN_CLR              0x0010061AB0
#define A_GPIO_PIN_SET              0x0010061AB8

#define A_GPIO_BASE		    0x0010061A80

#define R_GPIO_CLR_EDGE             0x00
#define R_GPIO_INT_TYPE             0x08
#define R_GPIO_INPUT_INVERT         0x10
#define R_GPIO_GLITCH               0x18
#define R_GPIO_READ                 0x20
#define R_GPIO_DIRECTION            0x28
#define R_GPIO_PIN_CLR              0x30
#define R_GPIO_PIN_SET              0x38

/*  ********************************************************************* 
    * SMBus Registers
    ********************************************************************* */

#define A_SMB_XTRA_0                0x0010060000
#define A_SMB_XTRA_1                0x0010060008
#define A_SMB_FREQ_0                0x0010060010
#define A_SMB_FREQ_1                0x0010060018
#define A_SMB_STATUS_0              0x0010060020
#define A_SMB_STATUS_1              0x0010060028
#define A_SMB_CMD_0                 0x0010060030
#define A_SMB_CMD_1                 0x0010060038
#define A_SMB_START_0               0x0010060040
#define A_SMB_START_1               0x0010060048
#define A_SMB_DATA_0                0x0010060050
#define A_SMB_DATA_1                0x0010060058
#define A_SMB_CONTROL_0             0x0010060060
#define A_SMB_CONTROL_1             0x0010060068
#define A_SMB_PEC_0                 0x0010060070