📄 sb1250_dma.h
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/* ********************************************************************* * SB1250 Board Support Package * * DMA definitions File: sb1250_dma.h * * This module contains constants and macros useful for * programming the SB1250's DMA controllers, both the data mover * and the Ethernet DMA. * * SB1250 specification level: User's manual 1/02/02 * * Author: Mitch Lichtenberg * ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */#ifndef _SB1250_DMA_H#define _SB1250_DMA_H#include "sb1250_defs.h"/* ********************************************************************* * DMA Registers ********************************************************************* *//* * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 * Registers: DMA_CONFIG0_SER_x_RX * Registers: DMA_CONFIG0_SER_x_TX */#define M_DMA_DROP _SB_MAKEMASK1(0)#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)#define S_DMA_DESC_TYPE _SB_MAKE64(1)#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE)#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)#define K_DMA_DESC_TYPE_RING_AL 0#define K_DMA_DESC_TYPE_CHAIN_AL 1#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define K_DMA_DESC_TYPE_RING_UAL_WI 2#define K_DMA_DESC_TYPE_RING_UAL_RMW 3#endif /* 1250 PASS3 || 112x PASS1 */#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)#define M_DMA_TBX_EN _SB_MAKEMASK1(6)#define M_DMA_TDX_EN _SB_MAKEMASK1(7)#define S_DMA_INT_PKTCNT _SB_MAKE64(8)#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)#define S_DMA_RINGSZ _SB_MAKE64(16)#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ)#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ)#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)/* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 * Registers: DMA_CONFIG1_SER_x_RX * Registers: DMA_CONFIG1_SER_x_TX */#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)#define M_DMA_L2CA _SB_MAKEMASK1(5)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)#endif /* 1250 PASS3 || 112x PASS1 */#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)#define S_DMA_HDR_SIZE _SB_MAKE64(21)#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE)#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)#define M_DMA_MBZ2 _SB_MAKEMASK(5,32)#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)/* * Ethernet and Serial DMA Descriptor base address (Table 7-6) */#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0)/* * ASIC Mode Base Address (Table 7-7) */#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0)/* * DMA Descriptor Count Registers (Table 7-8) */ /* No bitfields *//* * Current Descriptor Address Register (Table 7-11) */#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)#endif /* 1250 PASS3 || 112x PASS1 *//* * Receive Packet Drop Registers */#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_DMA_OODLOST_RX _SB_MAKE64(0)#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)#endif /* 1250 PASS3 || 112x PASS1 *//* ********************************************************************* * DMA Descriptors ********************************************************************* *//* * Descriptor doubleword "A" (Table 7-12) */#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET)#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET)/* Note: Don't shift the address over, just mask it with the mask below */#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)#endif /* 1250 PASS3 || 112x PASS1 */#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)#endif /* 1250 PASS3 || 112x PASS1 */#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)/* * Descriptor doubleword "B" (Table 7-13) */#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)#endif /* 1250 PASS3 || 112x PASS1 */#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)/* Note: Don't shift the address over, just mask it with the mask below */#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)#endif /* 1250 PASS3 || 112x PASS1 */#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)/* * from pass2 some bits in dscr_b are also used for rx status */#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS)#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)/* * Ethernet Descriptor Status Bits (Table 7-15) */#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* Note: BADTCPCS is actually in DSCR_B options field */#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)#endif /* 1250 PASS2 || 112x PASS1 */#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)#endif /* 1250 PASS3 || 112x PASS1 */#define S_DMA_ETHRX_RXCH 53#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)⌨️ 快捷键说明
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