riva_hw.c

linux-2.4.29操作系统的源码

            chip->PGRAPH[0x00000B7C/4] = chip->PFB[0x000002BC/4];
            chip->PGRAPH[0x00000F40/4] = 0x10000000;
            chip->PGRAPH[0x00000F44/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00000040;
            chip->PGRAPH[0x00000F54/4] = 0x00000008;
            chip->PGRAPH[0x00000F50/4] = 0x00000200;
            for (i = 0; i < (3*16); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00000040;
            chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00000800;
            for (i = 0; i < (16*16); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F40/4] = 0x30000000;
            chip->PGRAPH[0x00000F44/4] = 0x00000004;
            chip->PGRAPH[0x00000F50/4] = 0x00006400;
            for (i = 0; i < (59*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00006800;
            for (i = 0; i < (47*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00006C00;
            for (i = 0; i < (3*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00007000;
            for (i = 0; i < (19*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00007400;
            for (i = 0; i < (12*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00007800;
            for (i = 0; i < (12*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00004400;
            for (i = 0; i < (8*4); i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00000000;
            for (i = 0; i < 16; i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;
            chip->PGRAPH[0x00000F50/4] = 0x00000040;
            for (i = 0; i < 4; i++)
                chip->PGRAPH[0x00000F54/4] = 0x00000000;

	    if (chip->flatPanel) {
		VGA_WR08(chip->PCIO, 0x3d4, 0x53);
		VGA_WR08(chip->PCIO, 0x3d5, 0);
		VGA_WR08(chip->PCIO, 0x3d4, 0x54);
		VGA_WR08(chip->PCIO, 0x3d5, 0);
		VGA_WR08(chip->PCIO, 0x3d4, 0x21);
		VGA_WR08(chip->PCIO, 0x3d5, 0xfa);
	    }
            break;
    }
    LOAD_FIXED_STATE(Riva,FIFO);
    UpdateFifoState(chip);
    /*
     * Load HW mode state.
     */
    VGA_WR08(chip->PCIO, 0x03D4, 0x19);
    VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
    VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
    VGA_WR08(chip->PCIO, 0x03D4, 0x25);
    VGA_WR08(chip->PCIO, 0x03D5, state->screen);
    VGA_WR08(chip->PCIO, 0x03D4, 0x28);
    VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
    VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
    VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
    VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
    VGA_WR08(chip->PCIO, 0x03D4, 0x20);
    VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
    VGA_WR08(chip->PCIO, 0x03D4, 0x30);
    VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
    VGA_WR08(chip->PCIO, 0x03D4, 0x31);
    VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
    VGA_WR08(chip->PCIO, 0x03D4, 0x41);
    VGA_WR08(chip->PCIO, 0x03D5, state->extra);

    if (!chip->flatPanel) {
        chip->PRAMDAC[0x00000508/4]  = state->vpll;
        chip->PRAMDAC[0x00000520/4]  = state->vpll2;
        chip->PRAMDAC[0x0000050C/4]  = state->pllsel;
    } else {
	chip->PRAMDAC[0x00000848/4]  = state->scale;
    }
    chip->PRAMDAC[0x00000300/4]  = state->cursor2;
    chip->PRAMDAC[0x00000508/4]  = state->vpll;
    chip->PRAMDAC[0x0000050C/4]  = state->pllsel;
    chip->PRAMDAC[0x00000600/4]  = state->general;
    /*
     * Turn off VBlank enable and reset.
     */
    *(chip->VBLANKENABLE) = 0;
    *(chip->VBLANK)       = chip->VBlankBit;
    /*
     * Set interrupt enable.
     */    
    chip->PMC[0x00000140/4]  = chip->EnableIRQ & 0x01;
    /*
     * Set current state pointer.
     */
    chip->CurrentState = state;
    /*
     * Reset FIFO free and empty counts.
     */
    chip->FifoFreeCount  = 0;
    /* Free count from first subchannel */
    chip->FifoEmptyCount = chip->Rop->FifoFree; 
}
static void UnloadStateExt
(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state
)
{
    /*
     * Save current HW state.
     */
    VGA_WR08(chip->PCIO, 0x03D4, 0x19);
    state->repaint0     = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
    state->repaint1     = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x25);
    state->screen       = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x28);
    state->pixel        = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
    state->horiz        = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
    state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x20);
    state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x30);
    state->cursor0      = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x31);
    state->cursor1      = VGA_RD08(chip->PCIO, 0x03D5);
    VGA_WR08(chip->PCIO, 0x03D4, 0x41);
    state->extra        = VGA_RD08(chip->PCIO, 0x03D5);
    state->cursor2      = chip->PRAMDAC[0x00000300/4];
    state->vpll         = chip->PRAMDAC[0x00000508/4];
    state->vpll2        = chip->PRAMDAC[0x00000520/4];
    state->pllsel       = chip->PRAMDAC[0x0000050C/4];
    state->general      = chip->PRAMDAC[0x00000600/4];
    state->scale	= chip->PRAMDAC[0x00000848/4];
    state->config       = chip->PFB[0x00000200/4];
    switch (chip->Architecture)
    {
        case NV_ARCH_03:
            state->offset0  = chip->PGRAPH[0x00000630/4];
            state->offset1  = chip->PGRAPH[0x00000634/4];
            state->offset2  = chip->PGRAPH[0x00000638/4];
            state->offset3  = chip->PGRAPH[0x0000063C/4];
            state->pitch0   = chip->PGRAPH[0x00000650/4];
            state->pitch1   = chip->PGRAPH[0x00000654/4];
            state->pitch2   = chip->PGRAPH[0x00000658/4];
            state->pitch3   = chip->PGRAPH[0x0000065C/4];
            break;
        case NV_ARCH_04:
            state->offset0  = chip->PGRAPH[0x00000640/4];
            state->offset1  = chip->PGRAPH[0x00000644/4];
            state->offset2  = chip->PGRAPH[0x00000648/4];
            state->offset3  = chip->PGRAPH[0x0000064C/4];
            state->pitch0   = chip->PGRAPH[0x00000670/4];
            state->pitch1   = chip->PGRAPH[0x00000674/4];
            state->pitch2   = chip->PGRAPH[0x00000678/4];
            state->pitch3   = chip->PGRAPH[0x0000067C/4];
            break;
        case NV_ARCH_10:
	case NV_ARCH_20:
            state->offset0  = chip->PGRAPH[0x00000640/4];
            state->offset1  = chip->PGRAPH[0x00000644/4];
            state->offset2  = chip->PGRAPH[0x00000648/4];
            state->offset3  = chip->PGRAPH[0x0000064C/4];
            state->pitch0   = chip->PGRAPH[0x00000670/4];
            state->pitch1   = chip->PGRAPH[0x00000674/4];
            state->pitch2   = chip->PGRAPH[0x00000678/4];
            state->pitch3   = chip->PGRAPH[0x0000067C/4];
            break;
    }
}
static void SetStartAddress
(
    RIVA_HW_INST *chip,
    unsigned      start
)
{
    int offset = start >> 2;
    int pan    = (start & 3) << 1;
    unsigned char tmp;

    /*
     * Unlock extended registers.
     */
    chip->LockUnlock(chip, 0);
    /*
     * Set start address.
     */
    VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
    offset >>= 8;
    VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
    offset >>= 8;
    VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
    VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
    VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
    VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
    /*
     * 4 pixel pan register.
     */
    offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
    VGA_WR08(chip->PCIO, 0x3C0, 0x13);
    VGA_WR08(chip->PCIO, 0x3C0, pan);
}
static void nv3SetSurfaces2D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);

    RIVA_FIFO_FREE(*chip,Tri03,5);
    chip->FIFO[0x00003800] = 0x80000003;
    Surface->Offset        = surf0;
    chip->FIFO[0x00003800] = 0x80000004;
    Surface->Offset        = surf1;
    chip->FIFO[0x00003800] = 0x80000013;
}
static void nv4SetSurfaces2D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);

    chip->FIFO[0x00003800] = 0x80000003;
    Surface->Offset        = surf0;
    chip->FIFO[0x00003800] = 0x80000004;
    Surface->Offset        = surf1;
    chip->FIFO[0x00003800] = 0x80000014;
}
static void nv10SetSurfaces2D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);

    chip->FIFO[0x00003800] = 0x80000003;
    Surface->Offset        = surf0;
    chip->FIFO[0x00003800] = 0x80000004;
    Surface->Offset        = surf1;
    chip->FIFO[0x00003800] = 0x80000014;
}
static void nv3SetSurfaces3D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);

    RIVA_FIFO_FREE(*chip,Tri03,5);
    chip->FIFO[0x00003800] = 0x80000005;
    Surface->Offset        = surf0;
    chip->FIFO[0x00003800] = 0x80000006;
    Surface->Offset        = surf1;
    chip->FIFO[0x00003800] = 0x80000013;
}
static void nv4SetSurfaces3D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);

    chip->FIFO[0x00003800] = 0x80000005;
    Surface->Offset        = surf0;
    chip->FIFO[0x00003800] = 0x80000006;
    Surface->Offset        = surf1;
    chip->FIFO[0x00003800] = 0x80000014;
}
static void nv10SetSurfaces3D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]);

    RIVA_FIFO_FREE(*chip,Tri03,4);
    chip->FIFO[0x00003800]         = 0x80000007;
    Surfaces3D->RenderBufferOffset = surf0;
    Surfaces3D->ZBufferOffset      = surf1;
    chip->FIFO[0x00003800]         = 0x80000014;
}

/****************************************************************************\
*                                                                            *
*                      Probe RIVA Chip Configuration                         *
*                                                                            *
\****************************************************************************/

static void nv3GetConfig
(
    RIVA_HW_INST *chip
)
{
    /*
     * Fill in chip configuration.
     */
    if (chip->PFB[0x00000000/4] & 0x00000020)
    {
        if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
         && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
        {        
            /*
             * SDRAM 128 ZX.
             */
            chip->RamBandwidthKBytesPerSec = 800000;
            switch (chip->PFB[0x00000000/4] & 0x03)
            {
                case 2:
                    chip->RamAmountKBytes = 1024 * 4;
                    break;
                case 1:
                    chip->RamAmountKBytes = 1024 * 2;
                    break;
                default:
                    chip->RamAmountKBytes = 1024 * 8;
                    break;
            }
        }            
        else            
        {
            chip->RamBandwidthKBytesPerSec = 1000000;
            chip->RamAmountKBytes          = 1024 * 8;
        }            
    }
    else
    {
        /*
         * SGRAM 128.
         */
        chip->RamBandwidthKBytesPerSec = 1000000;
        switch (chip->PFB[0x00000000/4] & 0x00000003)
        {
            case 0:
                chip->RamAmountKBytes = 1024 * 8;
                break;
            case 2:
                chip->RamAmountKBytes = 1024 * 4;
                break;
            default:
                chip->RamAmountKBytes = 1024 * 2;
                break;
        }
    }        
    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000020) ? 14318 : 13500;
    chip->CURSOR           = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
    chip->VBLANKENABLE     = &(chip->PGRAPH[0x0140/4]);
    chip->VBLANK           = &(chip->PGRAPH