riva_hw.c

linux-2.4.29操作系统的源码

    else
    {
        lowM  = 7;
        highM = 13 - (chip->Architecture == NV_ARCH_03);
    }                      

    highP = 4 - (chip->Architecture == NV_ARCH_03);
    for (P = 0; P <= highP; P ++)
    {
        Freq = VClk << P;
        if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
        {
            for (M = lowM; M <= highM; M++)
            {
                N    = (VClk * M / chip->CrystalFreqKHz) << P;
                Freq = (chip->CrystalFreqKHz * N / M) >> P;
                if (Freq > VClk)
                    DeltaNew = Freq - VClk;
                else
                    DeltaNew = VClk - Freq;
                if (DeltaNew < DeltaOld)
                {
                    *mOut     = M;
                    *nOut     = N;
                    *pOut     = P;
                    *clockOut = Freq;
                    DeltaOld  = DeltaNew;
                }
            }
        }
    }
    return (DeltaOld != 0xFFFFFFFF);
}
/*
 * Calculate extended mode parameters (SVGA) and save in a 
 * mode state structure.
 */
static void CalcStateExt
(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state,
    int            bpp,
    int            width,
    int            hDisplaySize,
    int            hDisplay,
    int            hStart,
    int            hEnd,
    int            hTotal,
    int            height,
    int            vDisplay,
    int            vStart,
    int            vEnd,
    int            vTotal,
    int            dotClock
)
{
    int pixelDepth, VClk, m, n, p;
    /*
     * Save mode parameters.
     */
    state->bpp    = bpp;
    state->width  = width;
    state->height = height;
    /*
     * Extended RIVA registers.
     */
    pixelDepth = (bpp + 1)/8;
    CalcVClock(dotClock, hDisplaySize < 512,  /* double scan? */
               &VClk, &m, &n, &p, chip);

    switch (chip->Architecture)
    {
        case NV_ARCH_03:
            nv3UpdateArbitrationSettings(VClk, 
                                         pixelDepth * 8, 
                                        &(state->arbitration0),
                                        &(state->arbitration1),
                                         chip);
            state->cursor0  = 0x00;
            state->cursor1  = 0x78;
            state->cursor2  = 0x00000000;
            state->pllsel   = 0x10010100;
            state->config   = ((width + 31)/32)
                            | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
                            | 0x1000;
            state->general  = 0x00100100;
            state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
            break;
        case NV_ARCH_04:
            nv4UpdateArbitrationSettings(VClk, 
                                         pixelDepth * 8, 
                                        &(state->arbitration0),
                                        &(state->arbitration1),
                                         chip);
            state->cursor0  = 0x00;
            state->cursor1  = 0xFC;
            state->cursor2  = 0x00000000;
            state->pllsel   = 0x10000700;
            state->config   = 0x00001114;
            state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
            state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
            break;
        case NV_ARCH_10:
	case NV_ARCH_20:
            nv10UpdateArbitrationSettings(VClk, 
                                          pixelDepth * 8, 
                                         &(state->arbitration0),
                                         &(state->arbitration1),
                                          chip);
            state->cursor0  = 0x00;
            state->cursor1  = 0xFC;
            state->cursor2  = 0x00000000;
            state->pllsel   = 0x10000700;
            state->config   = chip->PFB[0x00000200/4];
            state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
            state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
            break;
    }
    state->vpll     = (p << 16) | (n << 8) | m;
    state->screen   = ((hTotal   & 0x040) >> 2)
                    | ((vDisplay & 0x400) >> 7)
                    | ((vStart   & 0x400) >> 8)
                    | ((vDisplay & 0x400) >> 9)
                    | ((vTotal   & 0x400) >> 10);
    state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
    state->horiz    = hTotal     < 260 ? 0x00 : 0x01;
    state->pixel    = pixelDepth > 2   ? 3    : pixelDepth;
    state->offset0  =
    state->offset1  =
    state->offset2  =
    state->offset3  = 0;
    state->pitch0   =
    state->pitch1   =
    state->pitch2   =
    state->pitch3   = pixelDepth * width;
}
/*
 * Load fixed function state and pre-calculated/stored state.
 */
#define LOAD_FIXED_STATE(tbl,dev)                                       \
    for (i = 0; i < sizeof(tbl##Table##dev)/8; i++)                 \
        chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
#define LOAD_FIXED_STATE_8BPP(tbl,dev)                                  \
    for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++)            \
        chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
#define LOAD_FIXED_STATE_15BPP(tbl,dev)                                 \
    for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++)           \
        chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
#define LOAD_FIXED_STATE_16BPP(tbl,dev)                                 \
    for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++)           \
        chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
#define LOAD_FIXED_STATE_32BPP(tbl,dev)                                 \
    for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++)           \
        chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
static void UpdateFifoState
(
    RIVA_HW_INST  *chip
)
{
    int i;

    switch (chip->Architecture)
    {
        case NV_ARCH_04:
            LOAD_FIXED_STATE(nv4,FIFO);
            chip->Tri03 = 0L;
            chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
            break;
        case NV_ARCH_10:
	case NV_ARCH_20:
            /*
             * Initialize state for the RivaTriangle3D05 routines.
             */
            LOAD_FIXED_STATE(nv10tri05,PGRAPH);
            LOAD_FIXED_STATE(nv10,FIFO);
            chip->Tri03 = 0L;
            chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
            break;
    }
}
static void LoadStateExt
(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state
)
{
    int i;

    /*
     * Load HW fixed function state.
     */
    LOAD_FIXED_STATE(Riva,PMC);
    LOAD_FIXED_STATE(Riva,PTIMER);
    switch (chip->Architecture)
    {
        case NV_ARCH_03:
            /*
             * Make sure frame buffer config gets set before loading PRAMIN.
             */
            chip->PFB[0x00000200/4] = state->config;
            LOAD_FIXED_STATE(nv3,PFIFO);
            LOAD_FIXED_STATE(nv3,PRAMIN);
            LOAD_FIXED_STATE(nv3,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                case 16:
                    LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
            }
            for (i = 0x00000; i < 0x00800; i++)
                chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
            chip->PGRAPH[0x00000630/4] = state->offset0;
            chip->PGRAPH[0x00000634/4] = state->offset1;
            chip->PGRAPH[0x00000638/4] = state->offset2;
            chip->PGRAPH[0x0000063C/4] = state->offset3;
            chip->PGRAPH[0x00000650/4] = state->pitch0;
            chip->PGRAPH[0x00000654/4] = state->pitch1;
            chip->PGRAPH[0x00000658/4] = state->pitch2;
            chip->PGRAPH[0x0000065C/4] = state->pitch3;
            break;
        case NV_ARCH_04:
            /*
             * Make sure frame buffer config gets set before loading PRAMIN.
             */
            chip->PFB[0x00000200/4] = state->config;
            LOAD_FIXED_STATE(nv4,PFIFO);
            LOAD_FIXED_STATE(nv4,PRAMIN);
            LOAD_FIXED_STATE(nv4,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                    LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 16:
                    LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
            }
            chip->PGRAPH[0x00000640/4] = state->offset0;
            chip->PGRAPH[0x00000644/4] = state->offset1;
            chip->PGRAPH[0x00000648/4] = state->offset2;
            chip->PGRAPH[0x0000064C/4] = state->offset3;
            chip->PGRAPH[0x00000670/4] = state->pitch0;
            chip->PGRAPH[0x00000674/4] = state->pitch1;
            chip->PGRAPH[0x00000678/4] = state->pitch2;
            chip->PGRAPH[0x0000067C/4] = state->pitch3;
            break;
        case NV_ARCH_10:
	case NV_ARCH_20:
            LOAD_FIXED_STATE(nv10,PFIFO);
            LOAD_FIXED_STATE(nv10,PRAMIN);
            LOAD_FIXED_STATE(nv10,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                    LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 16:
                    LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
            }

	    if (chip->Architecture == NV_ARCH_10) {
            	chip->PGRAPH[0x00000640/4] = state->offset0;
            	chip->PGRAPH[0x00000644/4] = state->offset1;
            	chip->PGRAPH[0x00000648/4] = state->offset2;
            	chip->PGRAPH[0x0000064C/4] = state->offset3;
            	chip->PGRAPH[0x00000670/4] = state->pitch0;
            	chip->PGRAPH[0x00000674/4] = state->pitch1;
            	chip->PGRAPH[0x00000678/4] = state->pitch2;
            	chip->PGRAPH[0x0000067C/4] = state->pitch3;
            	chip->PGRAPH[0x00000680/4] = state->pitch3;
	    } else {
		chip->PGRAPH[0x00000820/4] = state->offset0;
		chip->PGRAPH[0x00000824/4] = state->offset1;
		chip->PGRAPH[0x00000828/4] = state->offset2;
		chip->PGRAPH[0x0000082C/4] = state->offset3;
		chip->PGRAPH[0x00000850/4] = state->pitch0;
		chip->PGRAPH[0x00000854/4] = state->pitch1;
		chip->PGRAPH[0x00000858/4] = state->pitch2;
		chip->PGRAPH[0x0000085C/4] = state->pitch3;
		chip->PGRAPH[0x00000860/4] = state->pitch3;
		chip->PGRAPH[0x00000864/4] = state->pitch3;
		chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
		chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
	    }

	    chip->PFB[0x00000240/4] = 0;
	    chip->PFB[0x00000244/4] = 0;
	    chip->PFB[0x00000248/4] = 0;
	    chip->PFB[0x0000024C/4] = 0;
	    chip->PFB[0x00000250/4] = 0;
	    chip->PFB[0x00000244/4] = 0;
	    chip->PFB[0x00000248/4] = 0;
	    chip->PFB[0x0000024C/4] = 0;

            chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];
            chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];
            chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4];
            chip->PGRAPH[0x00000B0C/4] = chip->PFB[0x0000024C/4];
            chip->PGRAPH[0x00000B10/4] = chip->PFB[0x00000250/4];
            chip->PGRAPH[0x00000B14/4] = chip->PFB[0x00000254/4];
            chip->PGRAPH[0x00000B18/4] = chip->PFB[0x00000258/4];
            chip->PGRAPH[0x00000B1C/4] = chip->PFB[0x0000025C/4];
            chip->PGRAPH[0x00000B20/4] = chip->PFB[0x00000260/4];
            chip->PGRAPH[0x00000B24/4] = chip->PFB[0x00000264/4];
            chip->PGRAPH[0x00000B28/4] = chip->PFB[0x00000268/4];
            chip->PGRAPH[0x00000B2C/4] = chip->PFB[0x0000026C/4];
            chip->PGRAPH[0x00000B30/4] = chip->PFB[0x00000270/4];
            chip->PGRAPH[0x00000B34/4] = chip->PFB[0x00000274/4];
            chip->PGRAPH[0x00000B38/4] = chip->PFB[0x00000278/4];
            chip->PGRAPH[0x00000B3C/4] = chip->PFB[0x0000027C/4];
            chip->PGRAPH[0x00000B40/4] = chip->PFB[0x00000280/4];
            chip->PGRAPH[0x00000B44/4] = chip->PFB[0x00000284/4];
            chip->PGRAPH[0x00000B48/4] = chip->PFB[0x00000288/4];
            chip->PGRAPH[0x00000B4C/4] = chip->PFB[0x0000028C/4];
            chip->PGRAPH[0x00000B50/4] = chip->PFB[0x00000290/4];
            chip->PGRAPH[0x00000B54/4] = chip->PFB[0x00000294/4];
            chip->PGRAPH[0x00000B58/4] = chip->PFB[0x00000298/4];
            chip->PGRAPH[0x00000B5C/4] = chip->PFB[0x0000029C/4];
            chip->PGRAPH[0x00000B60/4] = chip->PFB[0x000002A0/4];
            chip->PGRAPH[0x00000B64/4] = chip->PFB[0x000002A4/4];
            chip->PGRAPH[0x00000B68/4] = chip->PFB[0x000002A8/4];
            chip->PGRAPH[0x00000B6C/4] = chip->PFB[0x000002AC/4];
            chip->PGRAPH[0x00000B70/4] = chip->PFB[0x000002B0/4];
            chip->PGRAPH[0x00000B74/4] = chip->PFB[0x000002B4/4];
            chip->PGRAPH[0x00000B78/4] = chip->PFB[0x000002B8/4];