pc300_drv.c

linux-2.4.29操作系统的源码

	switch (conf->fr_mode) {
		case PC300_FR_MF_CRC4:
			pfalc->multiframe_mode = 1;
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
			cpc_writeb(falcbase + F_REG(FMR3, ch),
				   cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);

			/* MultiFrame Resynchronization */
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);

			/* Automatic Loss of Multiframe > 914 CRC errors */
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);

			/* S1 and SI1/SI2 spare Bits set to 1 */
			cpc_writeb(falcbase + F_REG(XSP, ch),
				   cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
			cpc_writeb(falcbase + F_REG(XSP, ch),
				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
			cpc_writeb(falcbase + F_REG(XSP, ch),
				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);

			/* Automatic Force Resynchronization */
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);

			/* Transmit Automatic Remote Alarm */
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);

			/* Transmit Spare Bits for National Use (Y, Sn, Sa) */
			cpc_writeb(falcbase + F_REG(XSW, ch),
				   cpc_readb(falcbase + F_REG(XSW, ch)) |
				   XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
			break;

		case PC300_FR_MF_NON_CRC4:
		case PC300_FR_D4:
			pfalc->multiframe_mode = 0;
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) & 
				   ~(FMR2_RFS1 | FMR2_RFS0));
			cpc_writeb(falcbase + F_REG(XSW, ch),
				   cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
			cpc_writeb(falcbase + F_REG(XSP, ch),
				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);

			/* Automatic Force Resynchronization */
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);

			/* Transmit Automatic Remote Alarm */
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);

			/* Transmit Spare Bits for National Use (Y, Sn, Sa) */
			cpc_writeb(falcbase + F_REG(XSW, ch),
				   cpc_readb(falcbase + F_REG(XSW, ch)) |
				   XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
			break;

		case PC300_FR_UNFRAMED:
			pfalc->multiframe_mode = 0;
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) & 
				   ~(FMR2_RFS1 | FMR2_RFS0));
			cpc_writeb(falcbase + F_REG(XSP, ch),
				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
			cpc_writeb(falcbase + F_REG(XSW, ch),
				   cpc_readb(falcbase + F_REG(XSW, ch)) & 
				   ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
			cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) |
				   (FMR2_RTM | FMR2_DAIS));
			cpc_writeb(falcbase + F_REG(FMR2, ch),
				   cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
			cpc_writeb(falcbase + F_REG(FMR1, ch),
				   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
			pfalc->sync = 1;
			cpc_writeb(falcbase + card->hw.cpld_reg2,
				   cpc_readb(falcbase + card->hw.cpld_reg2) |
				   (CPLD_REG2_FALC_LED2 << (2 * ch)));
			break;
	}

	/* No signaling */
	cpc_writeb(falcbase + F_REG(XSP, ch),
		   cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
	cpc_writeb(falcbase + F_REG(CCR1, ch), 0);

	cpc_writeb(falcbase + F_REG(LIM1, ch),
		   cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
	cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));

	/* Transmit Clock-Slot Offset */
	cpc_writeb(falcbase + F_REG(XC0, ch),
		   cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
	/* Transmit Time-slot Offset */
	cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
	/* Receive  Clock-Slot offset */
	cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
	/* Receive  Time-slot offset */
	cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);

	/* LOS Detection after 176 consecutive 0s */
	cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
	/* LOS Recovery after 22 ones in the time window of PCD */
	cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);

	cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);

	falc_close_all_timeslots(card, ch);
}

void falc_init_hdlc(pc300_t * card, int ch)
{
	uclong falcbase = card->hw.falcbase;
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;

	/* Enable transparent data transfer */
	if (conf->fr_mode == PC300_FR_UNFRAMED) {
		cpc_writeb(falcbase + F_REG(MODE, ch), 0);
	} else {
		cpc_writeb(falcbase + F_REG(MODE, ch),
			   cpc_readb(falcbase + F_REG(MODE, ch)) |
			   (MODE_HRAC | MODE_MDS2));
		cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
		cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
		cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
		cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
	}

	/* Tx/Rx reset  */
	falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);

	/* Enable interrupt sources */
	falc_intr_enable(card, ch);
}

void te_config(pc300_t * card, int ch)
{
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
	falc_t *pfalc = (falc_t *) & chan->falc;
	uclong falcbase = card->hw.falcbase;
	ucchar dummy;
	unsigned long flags;

	memset(pfalc, 0, sizeof(falc_t));
	switch (conf->media) {
		case IF_IFACE_T1:
			pfalc->num_channels = NUM_OF_T1_CHANNELS;
			pfalc->offset = 1;
			break;
		case IF_IFACE_E1:
			pfalc->num_channels = NUM_OF_E1_CHANNELS;
			pfalc->offset = 0;
			break;
	}
	if (conf->tslot_bitmap == 0xffffffffUL)
		pfalc->full_bandwidth = 1;
	else
		pfalc->full_bandwidth = 0;

	CPC_LOCK(card, flags);
	/* Reset the FALC chip */
	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
		   (CPLD_REG1_FALC_RESET << (2 * ch)));
	udelay(10000);
	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
		   ~(CPLD_REG1_FALC_RESET << (2 * ch)));

	if (conf->media == IF_IFACE_T1) {
		falc_init_t1(card, ch);
	} else {
		falc_init_e1(card, ch);
	}
	falc_init_hdlc(card, ch);
	if (conf->rx_sens == PC300_RX_SENS_SH) {
		cpc_writeb(falcbase + F_REG(LIM0, ch),
			   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
	} else {
		cpc_writeb(falcbase + F_REG(LIM0, ch),
			   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
	}
	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
		   ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));

	/* Clear all interrupt registers */
	dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
		cpc_readb(falcbase + F_REG(FISR1, ch)) +
		cpc_readb(falcbase + F_REG(FISR2, ch)) +
		cpc_readb(falcbase + F_REG(FISR3, ch));
	CPC_UNLOCK(card, flags);
}

void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
{
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
	falc_t *pfalc = (falc_t *) & chan->falc;
	uclong falcbase = card->hw.falcbase;

	/* Verify LOS */
	if (frs0 & FRS0_LOS) {
		if (!pfalc->red_alarm) {
			pfalc->red_alarm = 1;
			pfalc->los++;
			if (!pfalc->blue_alarm) {
				// EVENT_FALC_ABNORMAL
				if (conf->media == IF_IFACE_T1) {
					/* Disable this interrupt as it may otherwise interfere 
					 * with other working boards. */
					cpc_writeb(falcbase + F_REG(IMR0, ch), 
						   cpc_readb(falcbase + F_REG(IMR0, ch))
						   | IMR0_PDEN);
				}
				falc_disable_comm(card, ch);
				// EVENT_FALC_ABNORMAL
			}
		}
	} else {
		if (pfalc->red_alarm) {
			pfalc->red_alarm = 0;
			pfalc->losr++;
		}
	}

	if (conf->fr_mode != PC300_FR_UNFRAMED) {
		/* Verify AIS alarm */
		if (frs0 & FRS0_AIS) {
			if (!pfalc->blue_alarm) {
				pfalc->blue_alarm = 1;
				pfalc->ais++;
				// EVENT_AIS
				if (conf->media == IF_IFACE_T1) {
					/* Disable this interrupt as it may otherwise interfere with                       other working boards. */
					cpc_writeb(falcbase + F_REG(IMR0, ch),
						   cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
				}
				falc_disable_comm(card, ch);
				// EVENT_AIS
			}
		} else {
			pfalc->blue_alarm = 0;
		}

		/* Verify LFA */
		if (frs0 & FRS0_LFA) {
			if (!pfalc->loss_fa) {
				pfalc->loss_fa = 1;
				pfalc->lfa++;
				if (!pfalc->blue_alarm && !pfalc->red_alarm) {
					// EVENT_FALC_ABNORMAL
					if (conf->media == IF_IFACE_T1) {
						/* Disable this interrupt as it may otherwise 
						 * interfere with other working boards. */
						cpc_writeb(falcbase + F_REG(IMR0, ch),
							   cpc_readb(falcbase + F_REG(IMR0, ch))
							   | IMR0_PDEN);
					}
					falc_disable_comm(card, ch);
					// EVENT_FALC_ABNORMAL
				}
			}
		} else {
			if (pfalc->loss_fa) {
				pfalc->loss_fa = 0;
				pfalc->farec++;
			}
		}

		/* Verify LMFA */
		if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
			/* D4 or CRC4 frame mode */
			if (!pfalc->loss_mfa) {
				pfalc->loss_mfa = 1;
				pfalc->lmfa++;
				if (!pfalc->blue_alarm && !pfalc->red_alarm &&
				    !pfalc->loss_fa) {
					// EVENT_FALC_ABNORMAL
					if (conf->media == IF_IFACE_T1) {
						/* Disable this interrupt as it may otherwise 
						 * interfere with other working boards. */
						cpc_writeb(falcbase + F_REG(IMR0, ch),
							   cpc_readb(falcbase + F_REG(IMR0, ch))
							   | IMR0_PDEN);
					}
					falc_disable_comm(card, ch);
					// EVENT_FALC_ABNORMAL
				}
			}
		} else {
			pfalc->loss_mfa = 0;
		}

		/* Verify Remote Alarm */
		if (frs0 & FRS0_RRA) {
			if (!pfalc->yellow_alarm) {
				pfalc->yellow_alarm = 1;
				pfalc->rai++;
				if (pfalc->sync) {
					// EVENT_RAI
					falc_disable_comm(card, ch);
					// EVENT_RAI
				}
			}
		} else {
			pfalc->yellow_alarm = 0;
		}
	} /* if !PC300_UNFRAMED */

	if (pfalc->red_alarm || pfalc->loss_fa ||
	    pfalc->loss_mfa || pfalc->blue_alarm) {
		if (pfalc->sync) {
			pfalc->sync = 0;
			chan->d.line_off++;
			cpc_writeb(falcbase + card->hw.cpld_reg2,
				   cpc_readb(falcbase + card->hw.cpld_reg2) &
				   ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
		}
	} else {
		if (!pfalc->sync) {
			pfalc->sync = 1;
			chan->d.line_on++;
			cpc_writeb(falcbase + card->hw.cpld_reg2,
				   cpc_readb(falcbase + card->hw.cpld_reg2) |
				   (CPLD_REG2_FALC_LED2 << (2 * ch)));
		}
	}

	if (pfalc->sync && !pfalc->yellow_alarm) {
		if (!pfalc->active) {
			// EVENT_FALC_NORMAL
			if (pfalc->loop_active) {
				return;
			}
			if (conf->media == IF_IFACE_T1) {
				cpc_writeb(falcbase + F_REG(IMR0, ch),
					   cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
			}
			falc_enable_comm(card, ch);
			// EVENT_FALC_NORMAL
			pfalc->active = 1;
		}
	} else {
		if (pfalc->active) {
			pfalc->active = 0;
		}
	}
}

void falc_update_stats(pc300_t * card, int ch)
{
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
	falc_t *pfalc = (falc_t *) & chan->falc;
	uclong falcbase = card->hw.falcbase;
	ucshort counter;

	counter = cpc_readb(falcbase + F_REG(FECL, ch));
	counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
	pfalc->fec += counter;

	counter = cpc_readb(falcbase + F_REG(CVCL, ch));
	counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
	pfalc->cvc += counter;

	counter = cpc_readb(falcbase + F_REG(CECL, ch));
	counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
	pfalc->cec += counter;

	counter = cpc_readb(falcbase + F_REG(EBCL, ch));
	counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
	pfalc->ebc += counter;

	if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
		mdelay(10);
		counter = cpc_readb(falcbase + F_REG(BECL, ch));
		counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
		pfalc->bec += counter;

		if (((conf->media == IF_IFACE_T1) &&
		     (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
		     (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
		    ||
		    ((conf->media == IF_IFACE_E1) &&
		     (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
			pfalc->prbs = 2;
		} else {
			pfalc->prbs = 1;
		}
	}
}

/*----------------------------------------------------------------------------
 * falc_remote_loop
 *----------------------------------------------------------------------------
 * Description:	In the remote loopback mode the clock and data recovered
 *		from the line inputs RL1/2 or RDIP/RDIN are routed back
 *		to the line outputs XL1/2 or XDOP/XDON via the analog
 *		transmitter. As in normal mode they are processsed by
 *		the synchronizer and then sent to the system interface.
 *----------------------------------------------------------------------------