setup.c

linux-2.4.29操作系统的源码

	strncpy(saved_command_line, *cmdline_p, sizeof(saved_command_line));
	saved_command_line[COMMAND_LINE_SIZE-1] = '\0';		/* for safety */

	efi_init();

#ifdef CONFIG_ACPI_BOOT
	/* Initialize the ACPI boot-time table parser */
	acpi_table_init();

# ifdef CONFIG_ACPI_NUMA
	acpi_numa_init();
# endif
#else
# ifdef CONFIG_SMP
	smp_build_cpu_map();	/* happens, e.g., with the Ski simulator */
# endif
#endif /* CONFIG_APCI_BOOT */

	iomem_resource.end = ~0UL;	/* FIXME probably belongs elsewhere */
	find_memory();

#if 0
	/* XXX fix me */
	init_mm.start_code = (unsigned long) &_stext;
	init_mm.end_code = (unsigned long) &_etext;
	init_mm.end_data = (unsigned long) &_edata;
	init_mm.brk = (unsigned long) &_end;

	code_resource.start = virt_to_bus(&_text);
	code_resource.end = virt_to_bus(&_etext) - 1;
	data_resource.start = virt_to_bus(&_etext);
	data_resource.end = virt_to_bus(&_edata) - 1;
#endif

	/* process SAL system table: */
	ia64_sal_init(efi.sal_systab);

#ifdef CONFIG_IA64_GENERIC
	machvec_init(acpi_get_sysname());
#endif

	/*
	 *  Set `iobase' to the appropriate address in region 6 (uncached access range).
	 *
	 *  The EFI memory map is the "preferred" location to get the I/O port space base,
	 *  rather the relying on AR.KR0. This should become more clear in future SAL
	 *  specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
	 *  found in the memory map.
	 */
	phys_iobase = efi_get_iobase();
	if (phys_iobase)
		/* set AR.KR0 since this is all we use it for anyway */
		ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
	else {
		phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
		printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
		       "to AR.KR0\n");
		printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
	}
	ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);

	/* setup legacy IO port space */
	io_space[0].mmio_base = ia64_iobase;
	io_space[0].sparse = 1;
	num_io_spaces = 1;

#ifdef CONFIG_SMP
	cpu_physical_id(0) = hard_smp_processor_id();
#endif

	cpu_init();	/* initialize the bootstrap CPU */

#ifdef CONFIG_ACPI_BOOT
	acpi_boot_init();
#endif
#ifdef CONFIG_SERIAL_HCDP
	if (efi.hcdp) {
		void setup_serial_hcdp(void *);

		/* Setup the serial ports described by HCDP */
		setup_serial_hcdp(efi.hcdp);
	}
#endif
#ifdef CONFIG_VT
# if defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
# endif
# if defined(CONFIG_VGA_CONSOLE)
	/*
	 * Non-legacy systems may route legacy VGA MMIO range to system
	 * memory.  vga_con probes the MMIO hole, so memory looks like
	 * a VGA device to it.  The EFI memory map can tell us if it's
	 * memory so we can avoid this problem.
	 */
	if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
		conswitchp = &vga_con;
# endif
#endif

#ifdef CONFIG_IA64_MCA
	/* enable IA-64 Machine Check Abort Handling */
	ia64_mca_init();
#endif

	platform_setup(cmdline_p);
	paging_init();

	unw_create_gate_table();
}

/*
 * Display cpu info for all cpu's.
 */
static int
show_cpuinfo (struct seq_file *m, void *v)
{
#ifdef CONFIG_SMP
#	define lpj	c->loops_per_jiffy
#	define cpu	c->processor
#else
#	define lpj	loops_per_jiffy
#	define cpu	0
#endif
	char family[32], features[128], *cp;
	struct cpuinfo_ia64 *c = v;
	unsigned long mask;

	mask = c->features;

	switch (c->family) {
	      case 0x07:	memcpy(family, "Itanium", 8); break;
	      case 0x1f:	memcpy(family, "Itanium 2", 10); break;
	      default:		sprintf(family, "%u", c->family); break;
	}

	/* build the feature string: */
	memcpy(features, " standard", 10);
	cp = features;
	if (mask & 1) {
		strcpy(cp, " branchlong");
		cp = strchr(cp, '\0');
		mask &= ~1UL;
	}
	if (mask)
		sprintf(cp, " 0x%lx", mask);

	seq_printf(m,
		   "processor  : %d\n"
		   "vendor     : %s\n"
		   "arch       : IA-64\n"
		   "family     : %s\n"
		   "model      : %u\n"
		   "revision   : %u\n"
		   "archrev    : %u\n"
		   "features   :%s\n"	/* don't change this---it _is_ right! */
		   "cpu number : %lu\n"
		   "cpu regs   : %u\n"
		   "cpu MHz    : %lu.%06lu\n"
		   "itc MHz    : %lu.%06lu\n"
		   "BogoMIPS   : %lu.%02lu\n\n",
		   cpu, c->vendor, family, c->model, c->revision, c->archrev,
		   features, c->ppn, c->number,
		   c->proc_freq / 1000000, c->proc_freq % 1000000,
		   c->itc_freq / 1000000, c->itc_freq % 1000000,
		   lpj*HZ/500000, (lpj*HZ/5000) % 100);
	return 0;
#undef lpj
#undef cpu
}

static void *
c_start (struct seq_file *m, loff_t *pos)
{
#ifdef CONFIG_SMP
	while (*pos < NR_CPUS && !(cpu_online_map & (1UL << *pos)))
		++*pos;
#endif
	return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
}

static void *
c_next (struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return c_start(m, pos);
}

static void
c_stop (struct seq_file *m, void *v)
{
}

struct seq_operations cpuinfo_op = {
	.start =c_start,
	.next =	c_next,
	.stop =	c_stop,
	.show =	show_cpuinfo
};

void
identify_cpu (struct cpuinfo_ia64 *c)
{
	union {
		unsigned long bits[5];
		struct {
			/* id 0 & 1: */
			char vendor[16];

			/* id 2 */
			u64 ppn;		/* processor serial number */

			/* id 3: */
			unsigned number		:  8;
			unsigned revision	:  8;
			unsigned model		:  8;
			unsigned family		:  8;
			unsigned archrev	:  8;
			unsigned reserved	: 24;

			/* id 4: */
			u64 features;
		} field;
	} cpuid;
	pal_vm_info_1_u_t vm1;
	pal_vm_info_2_u_t vm2;
	pal_status_t status;
	unsigned long impl_va_msb = 50, phys_addr_size = 44;	/* Itanium defaults */
	int i;

	for (i = 0; i < 5; ++i)
		cpuid.bits[i] = ia64_get_cpuid(i);

	memcpy(c->vendor, cpuid.field.vendor, 16);
#ifdef CONFIG_SMP
	c->processor = smp_processor_id();
#endif
	c->ppn = cpuid.field.ppn;
	c->number = cpuid.field.number;
	c->revision = cpuid.field.revision;
	c->model = cpuid.field.model;
	c->family = cpuid.field.family;
	c->archrev = cpuid.field.archrev;
	c->features = cpuid.field.features;

	status = ia64_pal_vm_summary(&vm1, &vm2);
	if (status == PAL_STATUS_SUCCESS) {
		impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
		phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
	}
	printk(KERN_INFO "CPU %d: %lu virtual and %lu physical address bits\n",
	       smp_processor_id(), impl_va_msb + 1, phys_addr_size);
	c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
	c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
}

/*
 * cpu_init() initializes state that is per-CPU.  This function acts
 * as a 'CPU state barrier', nothing should get across.
 */
void
cpu_init (void)
{
	extern void __init ia64_mmu_init (void *);
	unsigned long num_phys_stacked;
	pal_vm_info_2_u_t vmi;
	unsigned int max_ctx;
	struct cpuinfo_ia64 *my_cpu_data;
#ifdef CONFIG_NUMA
	int cpu;

	/*
	 * If NUMA is configured, the cpu_data array is not preallocated. The boot cpu
	 * allocates entries for every possible cpu. As the remaining cpus come online,
	 * they reallocate a new cpu_data structure on their local node. This extra work
	 * is required because some boot code references all cpu_data structures
	 * before the cpus are actually started.
	 */
	for (cpu=0; cpu < NR_CPUS; cpu++)
		if (node_cpuid[cpu].phys_id == hard_smp_processor_id())
			break;
	my_cpu_data = _cpu_data[cpu];
	my_cpu_data->node_data->active_cpu_count++;

	for (cpu=0; cpu<NR_CPUS; cpu++)
		_cpu_data[cpu]->cpu_data[smp_processor_id()] = my_cpu_data;
#else
	my_cpu_data = cpu_data(smp_processor_id());
	my_cpu_data->mmu_gathers = &mmu_gathers[smp_processor_id()];
#endif

	/*
	 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
	 * ia64_mmu_init() yet.  And we can't call ia64_mmu_init() first because it
	 * depends on the data returned by identify_cpu().  We break the dependency by
	 * accessing cpu_data() the old way, through identity mapped space.
	 */
	identify_cpu(my_cpu_data);

#ifdef CONFIG_MCKINLEY
	{
#define FEATURE_SET 16
		struct ia64_pal_retval iprv;

		if (my_cpu_data->family == 0x1f) {

			PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);

			if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) {

				PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
				              (iprv.v1 | 0x80), FEATURE_SET, 0);
			}
		}
	}
#endif

	/* Clear the stack memory reserved for pt_regs: */
	memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));

	ia64_set_kr(IA64_KR_FPU_OWNER, 0);

	/*
	 * Initialize default control register to defer all speculative faults.  The
	 * kernel MUST NOT depend on a particular setting of these bits (in other words,
	 * the kernel must have recovery code for all speculative accesses).  Turn on
	 * dcr.lc as per recommendation by the architecture team.  Most IA-32 apps
	 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
	 * be fine).
	 */
	ia64_set_dcr(  IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
		     | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC);
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	ia64_mmu_init(my_cpu_data);

#ifdef CONFIG_IA32_SUPPORT
	/* initialize global ia32 state - CR0 and CR4 */
	asm volatile ("mov ar.cflg = %0" :: "r" (((ulong) IA32_CR4 << 32) | IA32_CR0));
#endif

	/* disable all local interrupt sources: */
	ia64_set_itv(1 << 16);
	ia64_set_lrr0(1 << 16);
	ia64_set_lrr1(1 << 16);
	ia64_set_pmv(1 << 16);
	ia64_set_cmcv(1 << 16);

	/* clear TPR & XTP to enable all interrupt classes: */
	ia64_set_tpr(0);
#ifdef CONFIG_SMP
	normal_xtp();
#endif

	/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
	if (ia64_pal_vm_summary(NULL, &vmi) == 0)
		max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
	else {
		printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
		max_ctx = (1U << 15) - 1;	/* use architected minimum */
	}
	while (max_ctx < ia64_ctx.max_ctx) {
		unsigned int old = ia64_ctx.max_ctx;
		if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
			break;
	}

	if (ia64_pal_rse_info(&num_phys_stacked, 0) != 0) {
		printk(KERN_WARNING "cpu_init: PAL RSE info failed, assuming 96 physical stacked regs\n");
		num_phys_stacked = 96;
	}
	local_cpu_data->phys_stacked_size_p8 = num_phys_stacked*8 + 8;

	platform_cpu_init();
}