toshiba_rbtx4927_setup.c

linux-2.4.29操作系统的源码

		tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
	}

	tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
	    PCI_COMMAND_MEMORY |
#ifdef TX4927_SUPPORT_COMMAND_IO
	    PCI_COMMAND_IO |
#endif
	    PCI_COMMAND_PARITY | PCI_COMMAND_SERR;

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       ":pci setup complete:\n");
      //tx4927_dump_pcic_settings();

	{
		struct pci_channel *p;
		int busno;

		busno = 0;
		for (p = mips_pci_channels; p->pci_ops != NULL; p++) {
			busno = tx4927_pcibios_init(busno, p) + 1;
		}
	}

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
}

#endif /* CONFIG_PCI */

void toshiba_rbtx4927_restart(char *command)
{
	printk(KERN_NOTICE "System Rebooting...\n");

	/* enable the s/w reset register */
	reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);

	/* wait for enable to be seen */
	while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
		RBTX4927_SW_RESET_ENABLE_SET) == 0x00);

	/* do a s/w reset */
	reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);

	/* do something passive while waiting for reset */
	cli();
	while (1)
		asm_wait();

	/* no return */
}

void toshiba_rbtx4927_halt(void)
{
	printk(KERN_NOTICE "System Halted\n");
	cli();
	while (1) {
		asm_wait();
	}
	/* no return */
}

void toshiba_rbtx4927_power_off(void)
{
	toshiba_rbtx4927_halt();
	/* no return */
}

void toshiba_rbtx4927_nmi (struct pt_regs *regs)
{
	extern void show_code(unsigned int *pc);
	extern void show_runqueue(void);
	extern void show_stack(unsigned int *sp);
	extern void show_state_nolock(void);
	extern void show_trace(long *sp);

	bust_spinlocks(1);
	printk("\ncurrent = %d:%s\n",current->pid,current->comm);
	show_regs(regs);
	printk("Process %s (pid: %d, stackpage=%08lx)\n",
		current->comm, current->pid, (unsigned long) current);
	show_stack((unsigned int *)regs->regs[29]);
	show_trace((long *)regs->regs[29]);
	show_code((unsigned int *)regs->cp0_epc);
	bust_spinlocks(0);
}

void __init toshiba_rbtx4927_nmi_handler_setup (void)
{
	extern void tx4927_nmi_handler (void);
	unsigned long vec[2];

	vec[0] = 0x08000000 |
			(0x03ffffff & ((unsigned long)tx4927_nmi_handler >> 2));
	vec[1] = 0;

	/*
	 * Our firmware (PMON in this case) has a NMI hook that
	 * jumps to 0x80000220. We locate our NMI handler there.
	 */
	memcpy((void *)(KSEG0 + 0x220), &vec, 0x8);
}

void __init toshiba_rbtx4927_setup(void)
{
	extern void (*board_nmi_handler_setup)(void);
	vu32 cp0_config;

	printk("CPU is %s\n", toshiba_name);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       "-\n");

	/* f/w leaves this on at startup */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Clearing STO_ERL.\n");
	clear_c0_status(ST0_ERL);

	/* enable caches -- HCP5 does this, pmon does not */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
	cp0_config = read_c0_config();
	cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
	write_c0_config(cp0_config);

	/* set up the NMI handler */
	board_nmi_handler_setup = toshiba_rbtx4927_nmi_handler_setup;

#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
	{
		extern void dump_cp0(char *);
		dump_cp0("toshiba_rbtx4927_early_fw_fixup");
	}
#endif

	/* setup irq stuff */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Setting up tx4927 pic.\n");
	TX4927_WR(0xff1ff604, 0x00000400);	/* irq trigger */
	TX4927_WR(0xff1ff608, 0x00000000);	/* irq trigger */

	/* setup serial stuff */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Setting up tx4927 sio.\n");
	TX4927_WR(0xff1ff314, 0x00000000);	/* h/w flow control off */
	TX4927_WR(0xff1ff414, 0x00000000);	/* h/w flow control off */

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       "+\n");



	set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":mips_io_port_base=0x%08lx\n",
				       mips_io_port_base);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Resource\n");
	ioport_resource.start = 0;
	ioport_resource.end = 0xffffffff;
	iomem_resource.start = 0;
	iomem_resource.end = 0xffffffff;


	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":ResetRoutines\n");
	_machine_restart = toshiba_rbtx4927_restart;
	_machine_halt = toshiba_rbtx4927_halt;
	_machine_power_off = toshiba_rbtx4927_power_off;


#ifdef CONFIG_BLK_DEV_IDEPCI
	{
		TOSHIBA_RBTX4927_SETUP_DPRINTK
		    (TOSHIBA_RBTX4927_SETUP_SETUP,
		     ":ide_ops=&std_ide_ops(modified)\n");
		ide_ops = &std_ide_ops;
	}
#else
	{
		TOSHIBA_RBTX4927_SETUP_DPRINTK
		    (TOSHIBA_RBTX4927_SETUP_SETUP,
		     ":ide_ops=<NOT_CONFIG>\n");
	}
#endif

#ifdef CONFIG_FB
	{
		conswitchp = &dummy_con;
	}
#endif




#ifdef CONFIG_PCI

	/* PCIC */
	/*
	   * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	   * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
	   * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
	   * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
	   * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
	   * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
	   * i.e. S9[3]: ON (83MHz), OFF (100MHz)
	 */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
				       "ccfg is %lx, DIV is %x\n",
				       (unsigned long) tx4927_ccfgptr->
				       ccfg, TX4927_CCFG_PCIDIVMODE_MASK);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
				       "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCI66,
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCIMIDE,
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCIXARB);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
				       "PCIDIVMODE is %lx\n",
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCIDIVMODE_MASK);

	switch ((unsigned long) tx4927_ccfgptr->
		ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
	case TX4927_CCFG_PCIDIVMODE_2_5:
	case TX4927_CCFG_PCIDIVMODE_5:
		tx4927_cpu_clock = 166000000;	/* 166MHz */
		break;
	default:
		tx4927_cpu_clock = 200000000;	/* 200MHz */
	}

	/* CCFG */
	/* enable Timeout BusError */
	if (tx4927_ccfg_toeon)
		tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;

	/* SDRAMC fixup */
#ifdef CONFIG_TX4927BUG_WORKAROUND
	/*
	 * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
	 * G-bus timeout error detection is incorrect
	 */
	if (tx4927_ccfg_toeon)
		tx4927_sdramcptr->tr |= 0x02000000;	/* RCD:3tck */
#endif

#ifdef  TX4927_SUPPORT_PCI_66
	tx4927_pci66_setup();
#endif

	tx4927_pci_setup();


	{
		u32 id = 0;
		early_read_config_dword(&mips_pci_channels[0], 0, 0, 0x90,
					PCI_VENDOR_ID, &id);
		if (id == 0x94601055) {
			tx4927_using_backplane = 1;
			printk("backplane board IS installed\n");
		} else {
			printk("backplane board NOT installed\n");
		}
	}
#endif


	/* this is only done if backplane board installed, so must wait for pci */
#ifdef CONFIG_PC_KEYB
	{
		if (tx4927_using_backplane) {
			extern struct kbd_ops std_kbd_ops;
			kbd_ops = &std_kbd_ops;
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":kbd_ops=&std_kbd_ops\n");
		} else {
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":kbd_ops=<NO_BACKPLANE>\n");
		}
	}
#else
	{
		TOSHIBA_RBTX4927_SETUP_DPRINTK
		    (TOSHIBA_RBTX4927_SETUP_SETUP,
		     ":kbd_ops=<NOT_CONFIG>\n");
	}
#endif

	/* this is on ISA bus behind PCI bus, so need PCI up first */
#ifdef CONFIG_TOSHIBA_FPCIB0
	{
		if (tx4927_using_backplane) {
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":fpcibo=yes\n");

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_init()\n");
			smsc_fdc37m81x_init(0x3f0);

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_config_beg()\n");
			smsc_fdc37m81x_config_beg();

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_config_set(KBD)\n");
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
						  SMSC_FDC37M81X_KBD);
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
						  1);

			smsc_fdc37m81x_config_end();
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_config_end()\n");
		} else {
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":fpcibo=not_found\n");
		}
	}
#else
	{
		TOSHIBA_RBTX4927_SETUP_DPRINTK
		    (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
	}
#endif


	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       "+\n");
}

void __init
toshiba_rbtx4927_time_init(void)
{
#ifdef CONFIG_DS1742
	extern void rtc_ds1742_init(unsigned long base);
	extern void rtc_ds1742_wait(void);
	extern struct rtc_ops ds1742_rtc_ops;
	u32 c1;
	u32 c2;
#endif

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");

#ifdef CONFIG_DS1742

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":rtc_ds1742_init()-\n");
	rtc_ds1742_init(RBTX4927_IOC_NVRAMB_ADDR);
	rtc_ops = &ds1742_rtc_ops;

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":rtc_ds1742_init()+\n");

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":Calibrate mips_hpt_frequency-\n");
	rtc_ds1742_wait();

	/* get the count */
	c1 = read_c0_count();

	/* wait for the seconds to change again */
	rtc_ds1742_wait();

	/* get the count again */
	c2 = read_c0_count();

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":Calibrate mips_hpt_frequency+\n");
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":c1=%12u\n", c1);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":c2=%12u\n", c2);

	/* this diff is as close as we are going to get to counter ticks per sec */
	mips_hpt_frequency = abs(c2 - c1);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":f1=%12u\n", mips_hpt_frequency);

	/* round to 1/10th of a MHz */
	mips_hpt_frequency /= (100 * 1000);
	mips_hpt_frequency *= (100 * 1000);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
				       ":f2=%12u\n", mips_hpt_frequency);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
				       ":mips_hpt_frequency=%uHz (%uMHz)\n",
				       mips_hpt_frequency,
				       mips_hpt_frequency / 1000000);
#else
	mips_hpt_frequency = 100000000;
#endif

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");

}

void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
{
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
				       "-\n");
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
				       "+\n");
}