time.c

linux-2.4.29操作系统的源码

	u32 freq;
	struct timeval tv1, tv2;
	unsigned long diff_usec;
	unsigned long factor;

	/* Setup the timer:  We don't want to generate interrupts, just
	 * have it count down at its natural rate.
	 */
	ctrl_outb(0, TMU_TSTR);
#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif
	ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
	ctrl_outl(0xffffffff, TMU0_TCOR);
	ctrl_outl(0xffffffff, TMU0_TCNT);

	rtc_gettimeofday(&tv2);

	do {
		rtc_gettimeofday(&tv1);
	} while (tv1.tv_usec == tv2.tv_usec && tv1.tv_sec == tv2.tv_sec);

	/* actually start the timer */
	ctrl_outb(TMU0_TSTR_INIT, TMU_TSTR);

	do {
		rtc_gettimeofday(&tv2);
	} while (tv1.tv_usec == tv2.tv_usec && tv1.tv_sec == tv2.tv_sec);

	freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
	if (tv2.tv_usec < tv1.tv_usec) {
		tv2.tv_usec += 1000000;
		tv2.tv_sec--;
	}

	diff_usec = (tv2.tv_sec - tv1.tv_sec) * 1000000 + (tv2.tv_usec - tv1.tv_usec);

	/* this should work well if the RTC has a precision of n Hz, where
	 * n is an integer.  I don't think we have to worry about the other
	 * cases. */
	factor = (1000000 + diff_usec/2) / diff_usec;

	if (factor * diff_usec > 1100000 ||
	    factor * diff_usec <  900000)
		panic("weird RTC (diff_usec %ld)", diff_usec);

	return freq * factor;
}

static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ;
static int __init sh_pclk_setup(char *str)
{
	unsigned int freq;
	if (get_option(&str, &freq))
		sh_pclk_freq = freq;
	return 1;
}
__setup("sh_pclk=", sh_pclk_setup);

static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};

void __init time_init(void)
{
	unsigned int cpu_clock, master_clock, bus_clock, module_clock;
#ifdef CONFIG_CPU_SUBTYPE_ST40
	unsigned int memory_clock;
#endif
	unsigned int timer_freq;
	unsigned short frqcr, ifc, pfc, bfc;
	unsigned long interval;
#if defined(__sh3__)
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
	static int pfc_table[] = { 1, 2, 3, 4, 6 };
#else
	static int ifc_table[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
	static int pfc_table[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
	static int stc_table[] = { 1, 2, 4, 8, 3, 6, 1, 1 };
#endif
#elif defined(__SH4__)
	static int ifc_table[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
#define bfc_table ifc_table	/* Same */
	static int pfc_table[] = { 2, 3, 4, 6, 8, 2, 2, 2 };

#ifdef CONFIG_CPU_SUBTYPE_ST40
	struct frqcr_data {
		unsigned short frqcr;
		struct {
			unsigned char multiplier;
			unsigned char divisor;
		} factor[3];
	};

	static struct frqcr_data st40_frqcr_table[] = {		
		{ 0x000, {{1,1}, {1,1}, {1,2}}},
		{ 0x002, {{1,1}, {1,1}, {1,4}}},
		{ 0x004, {{1,1}, {1,1}, {1,8}}},
		{ 0x008, {{1,1}, {1,2}, {1,2}}},
		{ 0x00A, {{1,1}, {1,2}, {1,4}}},
		{ 0x00C, {{1,1}, {1,2}, {1,8}}},
		{ 0x011, {{1,1}, {2,3}, {1,6}}},
		{ 0x013, {{1,1}, {2,3}, {1,3}}},
		{ 0x01A, {{1,1}, {1,2}, {1,4}}},
		{ 0x01C, {{1,1}, {1,2}, {1,8}}},
		{ 0x023, {{1,1}, {2,3}, {1,3}}},
		{ 0x02C, {{1,1}, {1,2}, {1,8}}},
		{ 0x048, {{1,2}, {1,2}, {1,4}}},
		{ 0x04A, {{1,2}, {1,2}, {1,6}}},
		{ 0x04C, {{1,2}, {1,2}, {1,8}}},
		{ 0x05A, {{1,2}, {1,3}, {1,6}}},
		{ 0x05C, {{1,2}, {1,3}, {1,6}}},
		{ 0x063, {{1,2}, {1,4}, {1,4}}},
		{ 0x06C, {{1,2}, {1,4}, {1,8}}},
		{ 0x091, {{1,3}, {1,3}, {1,6}}},
		{ 0x093, {{1,3}, {1,3}, {1,6}}},
		{ 0x0A3, {{1,3}, {1,6}, {1,6}}},
		{ 0x0DA, {{1,4}, {1,4}, {1,8}}},
		{ 0x0DC, {{1,4}, {1,4}, {1,8}}},
		{ 0x0EC, {{1,4}, {1,8}, {1,8}}},
		{ 0x123, {{1,4}, {1,4}, {1,8}}},
		{ 0x16C, {{1,4}, {1,8}, {1,8}}},
	};

	struct memclk_data {
		unsigned char multiplier;
		unsigned char divisor;
	};
	static struct memclk_data st40_memclk_table[8] = {
		{1,1},	// 000
		{1,2},	// 001
		{1,3},	// 010
		{2,3},	// 011
		{1,4},	// 100
		{1,6},	// 101
		{1,8},	// 110
		{1,8}	// 111
	};
#endif
#endif

	if(rtc_gettimeofday)
		rtc_gettimeofday(&xtime);
	else{
        	xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
        	xtime.tv_usec = 0;
	}

	setup_irq(TIMER_IRQ, &irq0);

	if( sh_pclk_freq ){
		module_clock = sh_pclk_freq;
	}else{
		timer_freq = get_timer_frequency();
		module_clock = timer_freq * 4;
	}

#if defined(__sh3__)
	{
		unsigned short tmp;

		frqcr = ctrl_inw(FRQCR);
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
                bfc = ((frqcr & 0x0700) >> 8)+1;
                ifc = ((frqcr & 0x0070) >> 4)+1;
                tmp = frqcr & 0x0007;
                pfc = pfc_table[tmp];
#else
		tmp  = (frqcr & 0x8000) >> 13;
		tmp |= (frqcr & 0x0030) >>  4;
		bfc = stc_table[tmp];
		tmp  = (frqcr & 0x4000) >> 12;
		tmp |= (frqcr & 0x000c) >> 2;
		ifc  = ifc_table[tmp];
		tmp  = (frqcr & 0x2000) >> 11;
		tmp |= frqcr & 0x0003;
		pfc = pfc_table[tmp];
#endif
	}
#elif defined(__SH4__)
	{
#ifdef CONFIG_CPU_SUBTYPE_ST40
		unsigned long pvr;

		/* This should probably be moved into the SH3 probing code, and then use the processor
		 * structure to determine which CPU we are running on.
		 */
		pvr = ctrl_inl(CCN_PVR);
		printk("PVR %08x\n", pvr);

		if (((pvr >>CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1) {
			/* Unfortunatly the STB1 FRQCR values are different from the 7750 ones */
			struct frqcr_data *d;
			int a;
			unsigned long memclkcr;
			struct memclk_data *e;

			for (a=0; a<ARRAY_SIZE(st40_frqcr_table); a++) {
				d = &st40_frqcr_table[a];
				if (d->frqcr == (frqcr & 0x1ff))
					break;
			}
			if (a == ARRAY_SIZE(st40_frqcr_table)) {
				d = st40_frqcr_table;
				printk("ERROR: Unrecognised FRQCR value, using default multipliers\n");
			}

			memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR);
			e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK];

			printk("Clock multipliers: CPU: %d/%d Bus: %d/%d Mem: %d/%d Periph: %d/%d\n",
			       d->factor[0].multiplier, d->factor[0].divisor,
			       d->factor[1].multiplier, d->factor[1].divisor,
			       e->multiplier,           e->divisor,
			       d->factor[2].multiplier, d->factor[2].divisor);
			
			master_clock = module_clock * d->factor[2].divisor    / d->factor[2].multiplier;
			bus_clock    = master_clock * d->factor[1].multiplier / d->factor[1].divisor;
			memory_clock = master_clock * e->multiplier           / e->divisor;
			cpu_clock    = master_clock * d->factor[0].multiplier / d->factor[0].divisor;
			goto skip_calc;
		} else
#endif
		{
			frqcr = ctrl_inw(FRQCR);

			ifc  = ifc_table[(frqcr>> 6) & 0x0007];
			bfc  = bfc_table[(frqcr>> 3) & 0x0007];
			pfc = pfc_table[frqcr & 0x0007];
		}
	}
#endif
	master_clock = module_clock * pfc;
	bus_clock = master_clock / bfc;
	cpu_clock = master_clock / ifc;
#ifdef CONFIG_CPU_SUBTYPE_ST40
 skip_calc:
#endif
	printk("CPU clock: %d.%02dMHz\n",
	       (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
	printk("Bus clock: %d.%02dMHz\n",
	       (bus_clock/1000000), (bus_clock % 1000000)/10000);
#ifdef CONFIG_CPU_SUBTYPE_ST40
	printk("Memory clock: %d.%02dMHz\n",
	       (memory_clock/1000000), (memory_clock % 1000000)/10000);
#endif
	printk("Module clock: %d.%02dMHz\n",
	       (module_clock/1000000), (module_clock % 1000000)/10000);
	interval = (module_clock/4 + HZ/2) / HZ;

	printk("Interval = %ld\n", interval);

	current_cpu_data.cpu_clock    = cpu_clock;
	current_cpu_data.master_clock = master_clock;
	current_cpu_data.bus_clock    = bus_clock;
#ifdef CONFIG_CPU_SUBTYPE_ST40
	current_cpu_data.memory_clock = memory_clock;
#endif
	current_cpu_data.module_clock = module_clock;

	/* Stop all timers */
	ctrl_outb(0, TMU_TSTR);
#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif

	/* Start TMU0 (jiffy interrupts) */
	ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
	ctrl_outl(interval, TMU0_TCOR);
	ctrl_outl(interval, TMU0_TCNT);
	ctrl_outb(TMU0_TSTR_INIT, TMU_TSTR);

#if defined(CONFIG_START_TMU1)
	/* Start TMU1 (free-running) */
	ctrl_outw(TMU1_TCR_INIT, TMU1_TCR);
	ctrl_outl(0xffffffff, TMU1_TCOR);
	ctrl_outl(0xffffffff, TMU1_TCNT);
	ctrl_outb((ctrl_inb(TMU_TSTR) | TMU1_TSTR_INIT), TMU_TSTR);
#endif

#if defined(CONFIG_SH_KGDB)
	/*
	 * Set up kgdb as requested. We do it here because the serial
	 * init uses the timer vars we just set up for figuring baud.
	 */
        kgdb_init();
#endif

}