pci_st40.c

linux-2.4.29操作系统的源码

	/* Expose a 256M window starting at PCI address 0... */
	ST40PCI_WRITE(CSR_MBAR0, 0);
	ST40PCI_WRITE(LSR0, 0x0fff0001);

	/* ... and set up the initial incomming window to expose all of RAM */
	pci_set_rbar_region(7, memStart, memStart, memSize);

	/* Maximise timeout values */
	ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
	ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
	ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);

	ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING);

	return 1;
}

#define SET_CONFIG_BITS(bus,devfn,where)\
  (((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))

#define CONFIG_CMD(dev, where) SET_CONFIG_BITS((dev)->bus->number,(dev)->devfn,where)


static int CheckForMasterAbort(void)
{
	if (ST40PCI_READ(INT) & INT_MADIM) {
		/* Should we clear config space version as well ??? */
		ST40PCI_WRITE(INT, INT_MADIM);
		ST40PCI_WRITE_SHORT(CSR_STATUS, PCI_RMA);
		return 1;
	}

	return 0;
}

/* Write to config register */
static int st40pci_read_config_byte(struct pci_dev *dev, int where,
				    u8 * val)
{
	CheckForMasterAbort();

	ST40PCI_WRITE(PAR, CONFIG_CMD(dev, where));

	*val = ST40PCI_READ_BYTE(PDR + (where & 3));

	if (CheckForMasterAbort())
		*val = 0xff;


	return PCIBIOS_SUCCESSFUL;
}

static int st40pci_read_config_word(struct pci_dev *dev, int where,
				    u16 * val)
{
	CheckForMasterAbort();

	ST40PCI_WRITE(PAR, CONFIG_CMD(dev, where));

	*val = ST40PCI_READ_SHORT(PDR + (where & 2));

	if (CheckForMasterAbort())
		*val = 0xffff;

	return PCIBIOS_SUCCESSFUL;
}


static int st40pci_read_config_dword(struct pci_dev *dev, int where,
				     u32 * val)
{
	CheckForMasterAbort();

	ST40PCI_WRITE(PAR, CONFIG_CMD(dev, where));

	*val = ST40PCI_READ(PDR);

	if (CheckForMasterAbort()) {
		*val = 0xffffffff;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int st40pci_write_config_byte(struct pci_dev *dev, int where,
				     u8 val)
{
	ST40PCI_WRITE(PAR, CONFIG_CMD(dev, where));

	ST40PCI_WRITE_BYTE(PDR + (where & 3), val);

	CheckForMasterAbort();

	return PCIBIOS_SUCCESSFUL;
}


static int st40pci_write_config_word(struct pci_dev *dev, int where,
				     u16 val)
{
	ST40PCI_WRITE(PAR, CONFIG_CMD(dev, where));

	ST40PCI_WRITE_SHORT(PDR + (where & 2), val);

	CheckForMasterAbort();

	return PCIBIOS_SUCCESSFUL;
}

static int st40pci_write_config_dword(struct pci_dev *dev, int where,
				      u32 val)
{
	ST40PCI_WRITE(PAR, CONFIG_CMD(dev, where));

	ST40PCI_WRITE(PDR, val);

	CheckForMasterAbort();

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_config_ops = {
	st40pci_read_config_byte,
	st40pci_read_config_word,
	st40pci_read_config_dword,
	st40pci_write_config_byte,
	st40pci_write_config_word,
	st40pci_write_config_dword
};


/* Everything hangs off this */
static struct pci_bus *pci_root_bus;


static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
{
	printk("swizzle for dev %d on bus %d slot %d pin is %d\n",
	       dev->devfn,dev->bus->number, PCI_SLOT(dev->devfn),*pin);
	return PCI_SLOT(dev->devfn);
}

static inline u8 bridge_swizzle(u8 pin, u8 slot) 
{
	return (((pin-1) + slot) % 4) + 1;
}

u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
{
	if (dev->bus->number != 0) {
		u8 pin = *pinp;
		do {
			pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
			/* Move up the chain of bridges. */
			dev = dev->bus->self;
		} while (dev->bus->self);
		*pinp = pin;

		/* The slot is the slot of the last bridge. */
	}

	return PCI_SLOT(dev->devfn);
}

void __init
pcibios_fixup_pbus_ranges(struct pci_bus *bus,
			  struct pbus_set_ranges_data *ranges)
{
}

void __init pcibios_init(void)
{
	extern unsigned long memory_start, memory_end;

	if (sh_mv.mv_init_pci != NULL) {
		sh_mv.mv_init_pci();
	}

	/* The pci subsytem needs to know where memory is and how much 
	 * of it there is. I've simply made these globals. A better mechanism
	 * is probably needed.
	 */
	st40pci_init(PHYSADDR(memory_start),
		     PHYSADDR(memory_end) - PHYSADDR(memory_start));

	if (request_irq(ST40PCI_SERR_IRQ, st40_pci_irq, 
                        SA_INTERRUPT, "st40pci", NULL)) {
		printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
		return;
	}

	if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq, 
                        SA_INTERRUPT, "st40pci", NULL)) {
		printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
		return;
	}

	/* Reset state just in case any outstanding (usually SERR) */
        ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0); 
	/* Enable the PCI interrupts on the device */
	ST40PCI_WRITE(INTM, ~0);
	ST40PCI_WRITE(AINT, ~0);

	/* Map the io address apprioately */
#ifdef CONFIG_HD64465
	hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
			 ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
#endif

	/* ok, do the scan man */
	pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
	pci_assign_unassigned_resources();
	pci_fixup_irqs(no_swizzle, pcibios_map_platform_irq);

}

void __init
pcibios_fixup_resource(struct resource *res, struct resource *root)
{
        res->start += root->start;
        res->end += root->start;
}

void __init
pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
{
        /* Update device resources.  */
        int i;

        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
                if (!dev->resource[i].start)
                        continue;
                if (dev->resource[i].flags & IORESOURCE_IO)
                        pcibios_fixup_resource(&dev->resource[i],
                                               &pci_io_space);
                else if (dev->resource[i].flags & IORESOURCE_MEM)
                        pcibios_fixup_resource(&dev->resource[i],
                                               &pci_mem_space);
        }
}

void __init pcibios_fixup_bus(struct pci_bus *bus)
{
	/* Propogate hose info into the subordinate devices.  */
	struct list_head *ln;
	struct pci_dev *dev = bus->self;

	if (!dev) {
		bus->resource[0] = &pci_io_space;
		bus->resource[1] = &pci_mem_space;
	}

	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
		struct pci_dev *dev = pci_dev_b(ln);
		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			pcibios_fixup_device_resources(dev, bus);
	}
}

static void __init pcibios_assign_resources(void)
{
	struct pci_dev *dev;
	int idx;
	struct resource *r;
	pci_for_each_dev(dev) {
		int class = dev->class >> 8;

		/* Don't touch classless devices and host bridges */
		if (!class || class == PCI_CLASS_BRIDGE_HOST)
			continue;

		for(idx=0; idx<6; idx++) {
			r = &dev->resource[idx];

			/*
			 *  Don't touch IDE controllers and I/O ports of video cards!
			 */
			if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
			    (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
				continue;

			/*
			 *  We shall assign a new address to this resource, either because
			 *  the BIOS forgot to do so or because we have decided the old
			 *  address was unusable for some reason.
			 */
			if (!r->start && r->end)
                        {
                          	pci_assign_resource(dev, idx);
                         }
		}
#if 0 /* don't assign ROMs */
		if (pci_probe & PCI_ASSIGN_ROMS) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			r->end -= r->start;
			r->start = 0;
			if (r->end)
				pci_assign_resource(dev, PCI_ROM_RESOURCE);
		}
#endif
        }
}

/*
 * Publish a region of local address space over the PCI bus
 * to other devices.
 */
void pci_set_rbar_region(unsigned int region,     unsigned long localAddr,
			 unsigned long pciOffset, unsigned long regionSize)
{
	unsigned long mask;

	if (region > 7)
		return;

	if (regionSize > (512 * 1024 * 1024))
		return;

	mask = r2p2(regionSize) - 0x10000;

	/* Diable the region (in case currently in use, should never happen) */
	ST40PCI_WRITE_INDEXED(RSR, region, 0);

	/* Start of local address space to publish */
	ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) );

	/* Start of region in PCI address space as an offset from MBAR0 */
	ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset);

	/* Size of region */
	ST40PCI_WRITE_INDEXED(RSR, region, mask | 1);
} 

/*
 * Make a previously published region of local address space
 * inaccessible to other PCI devices.
 */ 
void pci_clear_rbar_region(unsigned int region)
{
	if (region > 7)
		return;

	ST40PCI_WRITE_INDEXED(RSR, region, 0);
	ST40PCI_WRITE_INDEXED(RBAR, region, 0);
	ST40PCI_WRITE_INDEXED(RLAR, region, 0);
}