📄 hal_resize.ps
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xld.w %r12,0x0000094e ; 2382
xcall halReadReg16
ld.uh %r10,%r10
.loc 277
xand %r10,%r10,0x00000003
.loc 278
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapEnSet, val CapEnSet, scl 2, type 0x21, endef
.global CapEnSet
.loc 292
.def ent, scl 101, type 0x0, endef
CapEnSet:
; .frame %sp,8,$31 # vars= 0, regs= 2/0, args= 0, extra= 0
; .mask 0x80010000,-4
; .fmask 0x00000000,0
pushn %r0
ld.w %r0,%r12
.def enable, val 0, scl 17, type 0xc, endef
.loc 293
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x00000960 ; 2400
xcall halReadReg16
.loc 294
xand %r10,%r10,0x0000fffe
.loc 295
ld.ub %r0,%r0
.loc 296
xld.w %r12,0x00000960 ; 2400
ld.w %r13,%r0
or %r13,%r10
xcall halWriteReg16
.loc 297
.def bend, scl 110, type 0x0, endef
popn %r0
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapEnGet, val CapEnGet, scl 2, type 0x2c, endef
.global CapEnGet
.loc 307
.def ent, scl 101, type 0x0, endef
CapEnGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 308
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x00000960 ; 2400
xcall halReadReg16
.loc 310
xand %r10,%r10,0x00000001
.loc 311
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapSWReset, val CapSWReset, scl 2, type 0x21, endef
.global CapSWReset
.loc 320
.def ent, scl 101, type 0x0, endef
CapSWReset:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 321
.def begin, scl 100, type 0x0, endef
.def capResizeCtl, val 10, scl 4, type 0xd, endef
xld.w %r12,0x00000960 ; 2400
xcall halReadReg16
.loc 322
xoor %r10,%r10,0x00000080
.loc 323
ld.uh %r10,%r10
xld.w %r12,0x00000960 ; 2400
ld.w %r13,%r10
xcall halWriteReg16
.loc 324
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapStartXPosSet, val CapStartXPosSet, scl 2, type 0x21, endef
.global CapStartXPosSet
.loc 333
.def ent, scl 101, type 0x0, endef
CapStartXPosSet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.def pos, val 12, scl 17, type 0xd, endef
.loc 334
ld.uh %r13,%r12
xld.w %r12,0x00000964 ; 2404
xcall halWriteReg16
.loc 335
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapStartXPosGet, val CapStartXPosGet, scl 2, type 0x2d, endef
.global CapStartXPosGet
.loc 344
.def ent, scl 101, type 0x0, endef
CapStartXPosGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 345
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x00000964 ; 2404
xcall halReadReg16
.loc 346
ld.uh %r10,%r10
.loc 347
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapStartYPosSet, val CapStartYPosSet, scl 2, type 0x21, endef
.global CapStartYPosSet
.loc 356
.def ent, scl 101, type 0x0, endef
CapStartYPosSet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.def pos, val 12, scl 17, type 0xd, endef
.loc 357
ld.uh %r13,%r12
xld.w %r12,0x00000966 ; 2406
xcall halWriteReg16
.loc 358
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapStartYPosGet, val CapStartYPosGet, scl 2, type 0x2d, endef
.global CapStartYPosGet
.loc 367
.def ent, scl 101, type 0x0, endef
CapStartYPosGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 368
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x00000966 ; 2406
xcall halReadReg16
.loc 369
ld.uh %r10,%r10
.loc 370
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapEndXPosSet, val CapEndXPosSet, scl 2, type 0x21, endef
.global CapEndXPosSet
.loc 380
.def ent, scl 101, type 0x0, endef
CapEndXPosSet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.def pos, val 12, scl 17, type 0xd, endef
.loc 381
ld.uh %r13,%r12
xld.w %r12,0x00000968 ; 2408
xcall halWriteReg16
.loc 382
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapEndXPosGet, val CapEndXPosGet, scl 2, type 0x2d, endef
.global CapEndXPosGet
.loc 391
.def ent, scl 101, type 0x0, endef
CapEndXPosGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 392
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x00000968 ; 2408
xcall halReadReg16
.loc 393
ld.uh %r10,%r10
.loc 394
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapEndYPosSet, val CapEndYPosSet, scl 2, type 0x21, endef
.global CapEndYPosSet
.loc 403
.def ent, scl 101, type 0x0, endef
CapEndYPosSet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.def pos, val 12, scl 17, type 0xd, endef
.loc 404
ld.uh %r13,%r12
xld.w %r12,0x0000096a ; 2410
xcall halWriteReg16
.loc 405
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapEndYPosGet, val CapEndYPosGet, scl 2, type 0x2d, endef
.global CapEndYPosGet
.loc 414
.def ent, scl 101, type 0x0, endef
CapEndYPosGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 415
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x0000096a ; 2410
xcall halReadReg16
.loc 416
ld.uh %r10,%r10
.loc 417
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapScalingRateGet, val CapScalingRateGet, scl 2, type 0x2c, endef
.global CapScalingRateGet
.loc 426
.def ent, scl 101, type 0x0, endef
CapScalingRateGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 427
.def begin, scl 100, type 0x0, endef
xld.w %r12,0x0000096c ; 2412
xcall halReadReg16
.loc 429
xand %r10,%r10,0x0000000f
.loc 430
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapScalingRateSet, val CapScalingRateSet, scl 2, type 0x21, endef
.global CapScalingRateSet
.loc 439
.def ent, scl 101, type 0x0, endef
CapScalingRateSet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.def scalingRate, val 12, scl 17, type 0xc, endef
.loc 441
ld.w %r13,%r12
xand %r13,%r13,0x0000000f
xld.w %r12,0x0000096c ; 2412
xcall halWriteReg16
.loc 442
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapScalingModeSet, val CapScalingModeSet, scl 2, type 0x21, endef
.global CapScalingModeSet
.loc 451
.def ent, scl 101, type 0x0, endef
CapScalingModeSet:
; .frame %sp,8,$31 # vars= 0, regs= 2/0, args= 0, extra= 0
; .mask 0x80010000,-4
; .fmask 0x00000000,0
pushn %r0
.def scalingMode, val 0, scl 17, tag __T20, size 4, type 0xa, endef
.loc 452
.def begin, scl 100, type 0x0, endef
.loc 453
ld.w %r0,%r12
xand %r0,%r0,0x00000003
.loc 455
xcall CapScalingRateGet
ld.ub %r10,%r10
xcmp %r10,2
xjrne __L42
.loc 457
xcmp %r0,3
xjreq __L41
xjrult __L42
xcmp %r0,7
xjrugt __L42
xcmp %r0,5
xjruge __L41
__L42:
.loc 467
xld.w %r12,0x0000096e ; 2414
xcall halReadReg16
.loc 468
xand %r10,%r10,0x0000fffc
.loc 470
xld.w %r12,0x0000096e ; 2414
ld.w %r13,%r10
or %r13,%r0
xcall halWriteReg16
.loc 471
.def bend, scl 110, type 0x0, endef
__L41:
popn %r0
ret
.def end, scl 111, type 0x0, endef
.align 1
.def CapScalingModeGet, val CapScalingModeGet, scl 2, tag __T20, size 4, type 0x2a, endef
.global CapScalingModeGet
.loc 480
.def ent, scl 101, type 0x0, endef
CapScalingModeGet:
; .frame %sp,4,$31 # vars= 0, regs= 1/0, args= 0, extra= 0
; .mask 0x80000000,-4
; .fmask 0x00000000,0
.loc 481
.def begin, scl 100, type 0x0, endef
.def scalingMode, val 10, scl 4, tag __T20, size 4, type 0xa, endef
xld.w %r12,0x0000096e ; 2414
xcall halReadReg16
ld.uh %r10,%r10
.loc 483
xand %r10,%r10,0x00000003
.loc 484
.def bend, scl 110, type 0x0, endef
ret
.def end, scl 111, type 0x0, endef
.endfile
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