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📄 hal_host.ps

📁 一款SmartPhone的驱动代码
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	xand	%r10,%r10,0x00000003
	xld.w	[%r1],%r10

	.loc	80
	.def	bend,	scl	110,	type	0x0,	endef
	popn	%r1
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	GetMemSize,	val	GetMemSize,	scl	2,	type	0x2f,	endef
	.global	GetMemSize

	.loc	90
	.def	ent,	scl	101,	type	0x0,	endef
GetMemSize:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0

	.loc	91
	.def	begin,	scl	100,	type	0x0,	endef
	.def	reg,	val	10,	scl	4,	type	0xf,	endef
	ld.w	%r12,0x0
	xcall	halReadReg16
	ld.uh	%r10,%r10

	.loc	92
	xsrl	%r10,8
	xsll	%r10,12

	.loc	93
	.def	bend,	scl	110,	type	0x0,	endef
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteReg8,	val	halWriteReg8,	scl	2,	type	0x21,	endef
	.global	halWriteReg8

	.loc	105
	.def	ent,	scl	101,	type	0x0,	endef
halWriteReg8:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	13,	scl	17,	type	0xc,	endef

	.loc	106
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjreq	__L11

	.loc	107
	ld.ub	%r13,%r13
	xcall	halIndirectWriteReg8
	xjp	__L12
__L11:

	.loc	109
	xld.w	%r10,[gHalRegAddr]
	add	%r10,%r12
	;.set	volatile
	xld.b	[%r10],%r13
	;.set	novolatile
__L12:

	.loc	111
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteReg16,	val	halWriteReg16,	scl	2,	type	0x21,	endef
	.global	halWriteReg16

	.loc	114
	.def	ent,	scl	101,	type	0x0,	endef
halWriteReg16:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	13,	scl	17,	type	0xd,	endef

	.loc	115
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjreq	__L14

	.loc	116
	ld.uh	%r13,%r13
	xcall	halIndirectWriteReg16
	xjp	__L15
__L14:

	.loc	118
	xld.w	%r10,[gHalRegAddr]
	add	%r10,%r12
	;.set	volatile
	xld.h	[%r10],%r13
	;.set	novolatile
__L15:

	.loc	120
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteReg32,	val	halWriteReg32,	scl	2,	type	0x21,	endef
	.global	halWriteReg32

	.loc	123
	.def	ent,	scl	101,	type	0x0,	endef
halWriteReg32:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	13,	scl	17,	type	0xf,	endef

	.loc	124
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjreq	__L17

	.loc	125
	xcall	halIndirectWriteReg32
	xjp	__L18
__L17:

	.loc	127
	xld.w	%r10,[gHalRegAddr]
	add	%r10,%r12
	;.set	volatile
	xld.w	[%r10],%r13
	;.set	novolatile
__L18:

	.loc	129
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadReg8,	val	halReadReg8,	scl	2,	type	0x2c,	endef
	.global	halReadReg8

	.loc	140
	.def	ent,	scl	101,	type	0x0,	endef
halReadReg8:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef

	.loc	141
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjrne	__L20

	.loc	144
	xld.w	%r10,[gHalRegAddr]
	add	%r10,%r12
	;.set	volatile
	xld.ub	%r10,[%r10]
	;.set	novolatile
	xjp	__L23
__L20:

	.loc	142
	xcall	halIndirectReadReg8
__L23:
	ld.ub	%r10,%r10

	.loc	145
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadReg16,	val	halReadReg16,	scl	2,	type	0x2d,	endef
	.global	halReadReg16

	.loc	148
	.def	ent,	scl	101,	type	0x0,	endef
halReadReg16:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef

	.loc	149
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjrne	__L25

	.loc	152
	xld.w	%r10,[gHalRegAddr]
	add	%r10,%r12
	;.set	volatile
	xld.uh	%r10,[%r10]
	;.set	novolatile
	xjp	__L28
__L25:

	.loc	150
	xcall	halIndirectReadReg16
__L28:
	ld.uh	%r10,%r10

	.loc	153
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadReg32,	val	halReadReg32,	scl	2,	type	0x2f,	endef
	.global	halReadReg32

	.loc	156
	.def	ent,	scl	101,	type	0x0,	endef
halReadReg32:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef

	.loc	157
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjrne	__L30

	.loc	160
	xld.w	%r10,[gHalRegAddr]
	add	%r10,%r12
	;.set	volatile
	xld.w	%r10,[%r10]
	;.set	novolatile
	xjp	__L32
__L30:

	.loc	158
	xcall	halIndirectReadReg32
__L32:

	.loc	161
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteDisplay8,	val	halWriteDisplay8,	scl	2,	type	0x21,	endef
	.global	halWriteDisplay8

	.loc	174
	.def	ent,	scl	101,	type	0x0,	endef
halWriteDisplay8:
;	.frame	%sp,8,$31		# vars= 0, regs= 2/0, args= 0, extra= 0
;	.mask	0x80010000,-4
;	.fmask	0x00000000,0
	pushn	%r0
	ld.w	%r0,%r13
	.def	Offset,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	0,	scl	17,	type	0xc,	endef

	.loc	175
	.def	begin,	scl	100,	type	0x0,	endef
	.def	pMem,	val	10,	scl	4,	type	0x1c,	endef

	.loc	177
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjreq	__L34

	.loc	179
	xcall	halIndirectWriteDisplayAddress

	.loc	180
	xld.w	%r10,[pIndirectData8]

	.loc	181
	xjp	__L36
__L34:

	.loc	184
	xld.w	%r10,[gHalMemAddr]
	add	%r12,%r10
	ld.w	%r10,%r12

	.loc	185
__L36:
	;.set	volatile
	xld.b	[%r10],%r0
	;.set	novolatile

	.loc	187
	.def	bend,	scl	110,	type	0x0,	endef
	popn	%r0
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteDisplay16,	val	halWriteDisplay16,	scl	2,	type	0x21,	endef
	.global	halWriteDisplay16

	.loc	190
	.def	ent,	scl	101,	type	0x0,	endef
halWriteDisplay16:
;	.frame	%sp,8,$31		# vars= 0, regs= 2/0, args= 0, extra= 0
;	.mask	0x80010000,-4
;	.fmask	0x00000000,0
	pushn	%r0
	ld.w	%r0,%r13
	.def	Offset,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	0,	scl	17,	type	0xd,	endef

	.loc	192
	.def	begin,	scl	100,	type	0x0,	endef
	.def	pMem,	val	10,	scl	4,	type	0x1d,	endef

	.loc	193
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjreq	__L38

	.loc	195
	xcall	halIndirectWriteDisplayAddress

	.loc	196
	xld.w	%r10,[pIndirectData16]

	.loc	197
	xjp	__L40
__L38:

	.loc	200
	xld.w	%r10,[gHalMemAddr]
	add	%r12,%r10
	ld.w	%r10,%r12

	.loc	201
__L40:
	;.set	volatile
	xld.h	[%r10],%r0
	;.set	novolatile

	.loc	203
	.def	bend,	scl	110,	type	0x0,	endef
	popn	%r0
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteDisplay32,	val	halWriteDisplay32,	scl	2,	type	0x21,	endef
	.global	halWriteDisplay32

	.loc	206
	.def	ent,	scl	101,	type	0x0,	endef
halWriteDisplay32:
;	.frame	%sp,8,$31		# vars= 0, regs= 2/0, args= 0, extra= 0
;	.mask	0x80010000,-4
;	.fmask	0x00000000,0
	pushn	%r0
	ld.w	%r0,%r13
	.def	Offset,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	0,	scl	17,	type	0xf,	endef

	.loc	207
	.def	begin,	scl	100,	type	0x0,	endef
	.def	pMem,	val	10,	scl	4,	type	0x1f,	endef

	.loc	208
	xld.w	%r10,[HalInfo+328]
	xand	%r10,%r10,0x00000040
	xjreq	__L42

	.loc	210
	xcall	halIndirectWriteDisplayAddress

	.loc	211
	xld.w	%r10,[pIndirectData8]
	xld.b	[%r10],%r0

	.loc	212
	xld.w	%r11,[pIndirectData8]
	ld.w	%r10,%r0
	xsrl	%r10,8
	xld.b	[%r11],%r10

	.loc	213
	xld.w	%r11,[pIndirectData8]
	ld.w	%r10,%r0
	xsrl	%r10,16
	xld.b	[%r11],%r10

	.loc	214
	xld.w	%r11,[pIndirectData8]
	ld.w	%r10,%r0
	xsrl	%r10,24
	xld.b	[%r11],%r10

	.loc	215
	xjp	__L43
__L42:

	.loc	218
	xld.w	%r10,[gHalMemAddr]
	add	%r12,%r10
	ld.w	%r10,%r12

	.loc	219
	;.set	volatile
	xld.w	[%r10],%r0
	;.set	novolatile
__L43:

	.loc	221
	.def	bend,	scl	110,	type	0x0,	endef
	popn	%r0
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadDisplay8,	val	halReadDisplay8,	scl	2,	type	0x2c,	endef
	.global	halReadDisplay8

	.loc	233
	.def	ent,	scl	101,	type	0x0,	endef
halReadDisplay8:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Offset,	val	12,	scl	17,	type	0xf,	endef
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