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📄 hal_host.ms

📁 一款SmartPhone的驱动代码
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	.loc	48
	.def	ent,	scl	101,	type	0x0,	endef
GetChipType:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0

	.loc	49
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	and	%r10,0x8	; 	xand	%r10,%r10,0x00000008
	jreq	__LX2		; 	xjreq	__L2

	.loc	50
	ld.w	%r10,0x0
	jp	__LX6		; 	xjp	__L6
__LX2:				; __L2:

	.loc	51
	ext	HalInfo+0x148@h	; 	xld.w	%r11,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r11,[%r9]
	and	%r11,0x10	; 	xand	%r11,%r11,0x00000010

	.loc	52
	ld.w	%r10,0x1	; 	xld.w	%r10,0x00000001		; 1

	.loc	51
	jrne	__LX6		; 	xjrne	__L6

	.loc	54
	ld.w	%r10,0x2	; 	xld.w	%r10,0x00000002		; 2

	.loc	52
__LX6:				; __L6:

	.loc	55
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	GetChipName,	val	GetChipName,	scl	2,	type	0x62,	endef
	.global	GetChipName

	.loc	64
	.def	ent,	scl	101,	type	0x0,	endef
GetChipName:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0

	.loc	65
	ext	HalInfo+0x114@h	; 	xld.w	%r10,HalInfo+276
	ext	HalInfo+0x114@m
	ld.w	%r10,HalInfo+0x114@l

	.loc	66
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	GetChipID,	val	GetChipID,	scl	2,	type	0x21,	endef
	.global	GetChipID

	.loc	75
	.def	ent,	scl	101,	type	0x0,	endef
GetChipID:
;	.frame	%sp,12,$31		# vars= 0, regs= 3/0, args= 0, extra= 0
;	.mask	0x80030000,-4
;	.fmask	0x00000000,0
	pushn	%r1
	ld.w	%r0,%r12
	ld.w	%r1,%r13
	.def	pProductCode,	val	0,	scl	17,	type	0x1f,	endef
	.def	pRevisionCode,	val	1,	scl	17,	type	0x1f,	endef

	.loc	76
	.def	begin,	scl	100,	type	0x0,	endef
	.def	Reg00,	val	10,	scl	4,	type	0xf,	endef
	ld.w	%r12,0x0
	call	halReadReg16	; 	xcall	halReadReg16
	ld.uh	%r10,%r10

	.loc	78
	ld.w	%r11,%r10
	srl	%r11,0x2	; 	xsrl	%r11,2
	ext	0x0		; 	xand	%r11,%r11,0x0000003f
	and	%r11,0x3f
	ld.w	[%r0],%r11	; 	xld.w	[%r0],%r11

	.loc	79
	and	%r10,0x3	; 	xand	%r10,%r10,0x00000003
	ld.w	[%r1],%r10	; 	xld.w	[%r1],%r10

	.loc	80
	.def	bend,	scl	110,	type	0x0,	endef
	popn	%r1
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	GetMemSize,	val	GetMemSize,	scl	2,	type	0x2f,	endef
	.global	GetMemSize

	.loc	90
	.def	ent,	scl	101,	type	0x0,	endef
GetMemSize:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0

	.loc	91
	.def	begin,	scl	100,	type	0x0,	endef
	.def	reg,	val	10,	scl	4,	type	0xf,	endef
	ld.w	%r12,0x0
	call	halReadReg16	; 	xcall	halReadReg16
	ld.uh	%r10,%r10

	.loc	92
	srl	%r10,0x8	; 	xsrl	%r10,8
	sll	%r10,0x8	; 	xsll	%r10,12
	sll	%r10,0x4

	.loc	93
	.def	bend,	scl	110,	type	0x0,	endef
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteReg8,	val	halWriteReg8,	scl	2,	type	0x21,	endef
	.global	halWriteReg8

	.loc	105
	.def	ent,	scl	101,	type	0x0,	endef
halWriteReg8:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	13,	scl	17,	type	0xc,	endef

	.loc	106
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	ext	0x1		; 	xand	%r10,%r10,0x00000040
	and	%r10,0x0
	jreq	__LX11		; 	xjreq	__L11

	.loc	107
	ld.ub	%r13,%r13
	ext	halIndirectWriteReg8@rm	; 	xcall	halIndirectWriteReg8
	call	halIndirectWriteReg8@rl
	jp	__LX12		; 	xjp	__L12
__LX11:				; __L11:

	.loc	109
	ext	gHalRegAddr+0x0@h	; 	xld.w	%r10,[gHalRegAddr]
	ext	gHalRegAddr+0x0@m
	ld.w	%r9,gHalRegAddr+0x0@l
	ld.w	%r10,[%r9]
	add	%r10,%r12
	;.set	volatile
	ld.b	[%r10],%r13	; 	xld.b	[%r10],%r13
	;.set	novolatile
__LX12:				; __L12:

	.loc	111
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteReg16,	val	halWriteReg16,	scl	2,	type	0x21,	endef
	.global	halWriteReg16

	.loc	114
	.def	ent,	scl	101,	type	0x0,	endef
halWriteReg16:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	13,	scl	17,	type	0xd,	endef

	.loc	115
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	ext	0x1		; 	xand	%r10,%r10,0x00000040
	and	%r10,0x0
	jreq	__LX14		; 	xjreq	__L14

	.loc	116
	ld.uh	%r13,%r13
	ext	halIndirectWriteReg16@rm	; 	xcall	halIndirectWriteReg16
	call	halIndirectWriteReg16@rl
	jp	__LX15		; 	xjp	__L15
__LX14:				; __L14:

	.loc	118
	ext	gHalRegAddr+0x0@h	; 	xld.w	%r10,[gHalRegAddr]
	ext	gHalRegAddr+0x0@m
	ld.w	%r9,gHalRegAddr+0x0@l
	ld.w	%r10,[%r9]
	add	%r10,%r12
	;.set	volatile
	ld.h	[%r10],%r13	; 	xld.h	[%r10],%r13
	;.set	novolatile
__LX15:				; __L15:

	.loc	120
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halWriteReg32,	val	halWriteReg32,	scl	2,	type	0x21,	endef
	.global	halWriteReg32

	.loc	123
	.def	ent,	scl	101,	type	0x0,	endef
halWriteReg32:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef
	.def	Value,	val	13,	scl	17,	type	0xf,	endef

	.loc	124
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	ext	0x1		; 	xand	%r10,%r10,0x00000040
	and	%r10,0x0
	jreq	__LX17		; 	xjreq	__L17

	.loc	125
	ext	halIndirectWriteReg32@rm	; 	xcall	halIndirectWriteReg32
	call	halIndirectWriteReg32@rl
	jp	__LX18		; 	xjp	__L18
__LX17:				; __L17:

	.loc	127
	ext	gHalRegAddr+0x0@h	; 	xld.w	%r10,[gHalRegAddr]
	ext	gHalRegAddr+0x0@m
	ld.w	%r9,gHalRegAddr+0x0@l
	ld.w	%r10,[%r9]
	add	%r10,%r12
	;.set	volatile
	ld.w	[%r10],%r13	; 	xld.w	[%r10],%r13
	;.set	novolatile
__LX18:				; __L18:

	.loc	129
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadReg8,	val	halReadReg8,	scl	2,	type	0x2c,	endef
	.global	halReadReg8

	.loc	140
	.def	ent,	scl	101,	type	0x0,	endef
halReadReg8:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef

	.loc	141
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	ext	0x1		; 	xand	%r10,%r10,0x00000040
	and	%r10,0x0
	jrne	__LX20		; 	xjrne	__L20

	.loc	144
	ext	gHalRegAddr+0x0@h	; 	xld.w	%r10,[gHalRegAddr]
	ext	gHalRegAddr+0x0@m
	ld.w	%r9,gHalRegAddr+0x0@l
	ld.w	%r10,[%r9]
	add	%r10,%r12
	;.set	volatile
	ld.ub	%r10,[%r10]	; 	xld.ub	%r10,[%r10]
	;.set	novolatile
	jp	__LX23		; 	xjp	__L23
__LX20:				; __L20:

	.loc	142
	ext	halIndirectReadReg8@rm	; 	xcall	halIndirectReadReg8
	call	halIndirectReadReg8@rl
__LX23:				; __L23:
	ld.ub	%r10,%r10

	.loc	145
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadReg16,	val	halReadReg16,	scl	2,	type	0x2d,	endef
	.global	halReadReg16

	.loc	148
	.def	ent,	scl	101,	type	0x0,	endef
halReadReg16:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef

	.loc	149
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	ext	0x1		; 	xand	%r10,%r10,0x00000040
	and	%r10,0x0
	jrne	__LX25		; 	xjrne	__L25

	.loc	152
	ext	gHalRegAddr+0x0@h	; 	xld.w	%r10,[gHalRegAddr]
	ext	gHalRegAddr+0x0@m
	ld.w	%r9,gHalRegAddr+0x0@l
	ld.w	%r10,[%r9]
	add	%r10,%r12
	;.set	volatile
	ld.uh	%r10,[%r10]	; 	xld.uh	%r10,[%r10]
	;.set	novolatile
	jp	__LX28		; 	xjp	__L28
__LX25:				; __L25:

	.loc	150
	ext	halIndirectReadReg16@rm	; 	xcall	halIndirectReadReg16
	call	halIndirectReadReg16@rl
__LX28:				; __L28:
	ld.uh	%r10,%r10

	.loc	153
	ret
	.def	end,	scl	111,	type	0x0,	endef
	.align	1
	.def	halReadReg32,	val	halReadReg32,	scl	2,	type	0x2f,	endef
	.global	halReadReg32

	.loc	156
	.def	ent,	scl	101,	type	0x0,	endef
halReadReg32:
;	.frame	%sp,4,$31		# vars= 0, regs= 1/0, args= 0, extra= 0
;	.mask	0x80000000,-4
;	.fmask	0x00000000,0
	.def	Index,	val	12,	scl	17,	type	0xf,	endef

	.loc	157
	ext	HalInfo+0x148@h	; 	xld.w	%r10,[HalInfo+328]
	ext	HalInfo+0x148@m
	ld.w	%r9,HalInfo+0x148@l
	ld.w	%r10,[%r9]
	ext	0x1		; 	xand	%r10,%r10,0x00000040
	and	%r10,0x0
	jrne	__LX30		; 	xjrne	__L30

	.loc	160
	ext	gHalRegAddr+0x0@h	; 	xld.w	%r10,[gHalRegAddr]
	ext	gHalRegAddr+0x0@m
	ld.w	%r9,gHalRegAddr+0x0@l
	ld.w	%r10,[%r9]
	add	%r10,%r12
	;.set	volatile
	ld.w	%r10,[%r10]	; 	xld.w	%r10,[%r10]
	;.set	novolatile
	jp	__LX32		; 	xjp	__L32
__LX30:				; __L30:

	.loc	158
	ext	halIndirectReadReg32@rm	; 	xcall	halIndirectReadReg32
	call	halIndirectReadReg32@rl
__LX32:				; __L32:
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