📄 reg137xx.h
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/************************************************************************
;
; Copyright (C) SEIKO EPSON CORP. 2002
;
; File Name: Register.h
; This is the address of register in 13712 & 13710
;
; Revision history
; 2002.11.12 D Eric Start.
;
;************************************************************************/
#ifndef __HAL_REG_H__
#define __HAL_REG_H__
#ifndef BOOL
#define BOOL unsigned char
#endif
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
#ifndef ON
#define ON 1
#define OFF 0
#endif
#ifndef NULL
#define NULL 0
#endif
//typedef unsigned char BOOL
#define REG_LCD_BASE 0x0000
// READ ONLY REGISTERS
#define REG0000_PRODUCT_INFORMATION 0x0000
#define REG0002_CONFIG_PINS_STATUS 0x0002
// CLOCK SSTTING REGISTERS
#define REG000E_PLL_SETTING0 0x000e
#define REG0010_PLL_SETTING1 0x0010
#define REG0012_PLL_SETTING2 0x0012
#define REG0014_POWER_SAVE_CONFIG 0x0014
#define REG0016_SOFTWARE_RESET 0x0016
#define REG0018_SYSTEM_CLOCK_SETTING 0x0018
// INDIRECT INTERFACE REGISTERS
#define REG0020_INDIRECT_COMMAND_READBACK 0x0020
#define REG0022_INDIRECT_MEM_ADDR1 0x0022
#define REG0024_INDIRECT_MEM_ADDR2 0x0024
#define REG0026_INDIRECT_AUTO_INC 0x0026
#define REG0028_INDIRECT_MEM_PORT 0x0028
#define REG002A_INDIRECT_2D_RDWR_PORT 0x002A
// LCD PANEL INTERFACE SETTING REGISTERS
#define REG0030_LCD_INTERFACE_CLOCK 0x0030
#define REG0032_LCD_MODULE_CLOCK 0x0032
#define REG0034_LCD_INTERFACE_COMMAND 0x0034
#define REG0036_LCD_INTERFACE_PARAMETER 0x0036
#define REG0038_LCD_INTERFACE_STATUS 0x0038
#define REG003A_LCD_INTERFACE_FRM_XFER 0x003a
#define REG003C_LCD_INTERFACE_TRANSFER 0x003c
// LCD1 SETTING REGISTERS
#define REG0040_LCD1_HORIZONTAL_TOTAL 0x0040
#define REG0042_LCD1_HDP 0x0042
#define REG0044_LCD1_HDP_START_POS 0x0044
#define REG0046_LCD1_FPLINE 0x0046
#define REG0048_LCD1_FPLINE_PULSE_POS 0x0048
#define REG004A_LCD1_VERTICAL_TOTAL 0x004a
#define REG004C_LCD1_VDP 0x004c
#define REG004E_LCD1_VDP_START_POS 0x004e
#define REG0050_LCD1_FPFRAME 0x0050
#define REG0052_LCD1_FPFRAME_PULSE_POS 0x0052
#define REG0054_LCD1_SERIAL_INTERFACE 0x0054
#define REG0056_LCD1_PARALLEL_INTERFACE 0x0056
// LCD2 SETTING REGISTERS
#define REG0058_LCD2_HDP 0x0058
#define REG005A_LCD2_VDP 0x005a
#define REG005C_LCD2_SERIAL_INTERFACE 0x005c
#define REG005E_LCD2_PARALLEL_INTERFACE 0x005e
// SERIAL VIDEO INTERFACE REGISTERS
#define REG0060_SERIAL_VIDEO_HDP 0x0060
#define REG0062_SERIAL_VIDEO_VDP 0x0062
#define REG0064_SERIAL_VIDEO_INTERFACE 0x0064
#define REG0066_SERIAL_VIDEO_HDR_REG0 0x0066
#define REG0068_SERIAL_VIDEO_HDR_REG1 0x0068
#define REG006A_SERIAL_VIDEO_HDR_REG2 0x006a
#define REG006C_SERIAL_VIDEO_HDR_REG3 0x006c
#define REG006E_SERIAL_VIDEO_HDR_REG4 0x006e
#define REG0070_SERIAL_VIDEO_HDR_REG5 0x0070
#define REG0072_SERIAL_VIDEO_HDR_REG6 0x0072
#define REG0074_SERIAL_VIDEO_HDR_REG7 0x0074
#define REG0076_SERIAL_VIDEO_FTR_REG0 0x0076
#define REG0078_SERIAL_VIDEO_FTR_REG1 0x0078
#define REG007A_SERIAL_VIDEO_FTR_REG2 0x007A
#define REG007C_SERIAL_VIDEO_FTR_REG3 0x007C
#define REG007E_SERIAL_VIDEO_STATUS 0x007E
#define REG0080_SERIAL_VIDEO_FRAME_XFER 0x0080
#define REG0082_SERIAL_VIDEO_FRAME_XFER 0x0082
// EXTENDED PANEL REGISTERS
#define REG0090_HRTFT_CONFIGURATION 0x0090
#define REG0092_HRTFT_CLS_WIDTH 0x0092
#define REG0094_HRTFT_PS1_RISING_EDGE 0x0094
#define REG0096_HRTFT_PS2_RISING_EDGE 0x0096
#define REG0098_HRTFT_PS2_TOGGLE_WIDTH 0x0098
#define REG009A_HRTFT_PS3_SIGNAL_WIDTH 0x009a
#define REG009E_HRTFT_REV_TOGGLE_POINT 0x009e
#define REG00A0_HRTFT_PS12_END 0x00a0
#define REG00A2_TYPE2_TFT_CONFIG 0x00a2
#define REG00A4_CASIO_TFT_TIMING_REG0 0x00a4
#define REG00A6_CASIO_TFT_TIMING_REG1 0x00a6
#define REG00A8_T3_TFT_CONFIG_REG0 0x00a8
#define REG00AA_T3_TFT_CONFIG_REG1 0x00aa
#define REG00AC_T3_TFT_CONFIG_REG2 0x00ac
#define REG00AE_T3_TFT_CONFIG_REG3 0x00ae
#define REG00B0_T3_TFT_PCLK_DIVIDE 0x00b0
#define REG00B2_T3_TFT_PRTL_MODE_CTRL 0x00b2
#define REG00B4_T3_TFT_PRTL_AREA0_POS0 0x00b4
#define REG00B6_T3_TFT_PRTL_AREA0_POS1 0x00b6
#define REG00B8_T3_TFT_PRTL_AREA1_POS0 0x00b8
#define REG00BA_T3_TFT_PRTL_AREA1_POS1 0x00ba
#define REG00BC_T3_TFT_PRTL_AREA2_POS0 0x00bc
#define REG00BE_T3_TFT_PRTL_AREA2_POS1 0x00be
#define REG00C0_T3_TFT_CMD_STORE0 0x00c0
#define REG00C2_T3_TFT_CMD_STORE1 0x00c2
#define REG00C4_TYPE3_TFT_MISC 0x00c4
#define REG00EE_PRTL_DRV_A0_START_LINE 0x00ee
#define REG00F0_PRTL_DRV_A0_END_LINE 0x00f0
#define REG00F2_PRTL_DRV_A1_START_LINE 0x00f2
#define REG00F4_PRTL_DRV_A1_END_LINE 0x00f4
// CAMERA INTERFACE REGISTERS
#define REG0100_CAM1_CLOCK_SETTING 0x0100
#define REG0102_CAM1_SIGNAL_SETTING 0x0102
#define REG0104_CAM2_CLOCK_DIVIDE_SEL 0x0104
#define REG0106_CAM2_INPUT_SIG_FMT_SEL 0x0106
#define REG0108_CAM1_TYPE2_VERT_COUNTER 0x0108
#define REG010A_CAM1_TYPE2_HORZ_COUNTER 0x010A
#define REG010C_CAM1_TYPE2_CONTROL 0x010C
#define REG010E_CAM1_TYPE2_STATUS 0x010E
#define REG0110_CAMERA_MODE_SETTING 0x0110
#define REG0112_CAMERA_FRAME_SETTING 0x0112
#define REG0114_CAMERA_CTRL 0x0114
#define REG0120_STROBO_LINE_DELAY 0x0120
#define REG0122_STROBO_PULSE_WIDTH 0x0122
#define REG0124_STROBO_SETTING 0x0124
#define REG0126_T3_ENABLE 0x0126
#define REG0128_T3_HEIGHT 0x0128
#define REG012A_T3_WIDTH 0x012a
// DISPLAY MODE SETTING REGISTERS
#define REG0200_DISPLAY_MODE_SETTING0 0x0200
#define REG0202_DISPLAY_MODE_SETTING1 0x0202
#define REG0204_OVERLAY_KEY_COL_RED 0x0204
#define REG0206_OVERLAY_KEY_COL_GREEN 0x0206
#define REG0208_OVERLAY_KEY_COL_BLUE 0x0208
#define REG0210_MWIN_DISP_START_ADDR0 0x0210
#define REG0212_MWIN_DISP_START_ADDR1 0x0212
#define REG0214_MWIN_START_ADDR 0x0214
#define REG0216_MWIN_LINE_ADDR_OFFSET 0x0216
#define REG0218_PIP_DISPLAY_START_ADDR0 0x0218
#define REG021A_PIP_DISPLAY_START_ADDR1 0x021a
#define REG021C_PIPWIN_START_ADDR_STATUS 0x021c
#define REG021E_PIPWIN_LINE_ADDR_OFFSET 0x021e
#define REG0220_PIP_X_START_POS 0x0220
#define REG0222_PIP_Y_START_POS 0x0222
#define REG0224_PIP_X_END_POS 0x0224
#define REG0226_PIP_Y_END_POS 0x0226
#define REG0228_PIP_START_FIELD 0x0228
#define REG0240_YUVRGB_TRANSLATE_MODE 0x0240
#define REG0242_YUV_WR_START_ADDR0REG0 0x0242
#define REG0244_YUV_WR_START_ADDR0REG1 0x0244
#define REG0246_YUV_WR_START_ADDR1REG0 0x0246
#define REG0248_YUV_WR_START_ADDR1REG1 0x0248
#define REG024A_UV_DATA_CLIP 0x024A
#define REG024C_DISPLAY_FIFO_THRESHOLD 0x024C
// GPIO REGISTERS
#define REG0300_GPIO_STATUS_CTRL0 0x0300
#define REG0302_GPIO_STATUS_CTRL1 0x0302
#define REG0304_GPIO_STATUS_CTRL2 0x0304
#define REG0306_GPIO_STATUS_CTRL3 0x0306
#define REG0308_GPIO_PULLDOWN_CTRL0 0x0308
#define REG030A_GPIO_PULLDOWN_CTRL1 0x030A
#define REG030C_GPIO_STATUS_CTRL4 0x030C
#define REG030E_GPIO_STATUS_CTRL5 0x030E
// OVERLAY REGISTERS
#define REG0310_AVG_OVERLAY_KEY_COL_RED 0x0310
#define REG0312_AVG_OVERLAY_KEY_COL_GREEN 0x0312
#define REG0314_AVG_OVERLAY_KEY_COL_BLUE 0x0314
#define REG0316_AND_OVERLAY_KEY_COL_RED 0x0316
#define REG0318_AND_OVERLAY_KEY_COL_GREEN 0x0318
#define REG031A_AND_OVERLAY_KEY_COL_BLUE 0x031A
#define REG031C_OR_OVERLAY_KEY_COL_RED 0x031C
#define REG031E_OR_OVERLAY_KEY_COL_GREEN 0x031E
#define REG0320_OR_OVERLAY_KEY_COL_BLUE 0x0320
#define REG0322_INV_OVERLAY_KEY_COL_RED 0x0322
#define REG0324_INV_OVERLAY_KEY_COL_GREEN 0x0324
#define REG0326_INV_OVERLAY_KEY_COL_BLUE 0x0326
#define REG0328_OVERLAY_MISCELLANEOUS 0x0328
// LOOK-UP TABLE REGISTERS
#define REG0400_LUT1_DATA0 0x0400
#define REG0402_LUT1_DATA1 0x0402
#define REG0800_LUT2_DATA0 0x0800
#define REG0802_LUT2_DATA1 0x0802
// RESIZE OPERATION REGISTERS
#define REG0930_GLOBAL_RESIZE_CTRL 0x0930
#define REG0940_VIEW_RESIZE_CTRL 0x0940
#define REG0944_VIEW_RESIZE_START_X_POS 0x0944
#define REG0946_VIEW_RESIZE_START_Y_POS 0x0946
#define REG0948_VIEW_RESIZE_END_X_POS 0x0948
#define REG094A_VIEW_RESIZE_END_Y_POS 0x094a
#define REG094C_VIEW_RESIZE_OP0 0x094c
#define REG094E_VIEW_RESIZE_OP1 0x094e
#define REG0950_VIEW_RESIZE_SHRINK_X 0x0950
#define REG0952_VIEW_RESIZE_SHRINK_Y 0x0952
#define REG0960_CAP_RESIZE_CTRL 0x0960
#define REG0964_CAP_RESIZE_START_X_POS 0x0964
#define REG0966_CAP_RESIZE_START_Y_POS 0x0966
#define REG0968_CAP_RESIZE_END_X_POS 0x0968
#define REG096A_CAP_RESIZE_END_Y_POS 0x096a
#define REG096C_CAP_RESIZE_OP0 0x096c
#define REG096E_CAP_RESIZE_OP1 0x096e
// JPEG FUNCTION REGISTERS
#define REG0980_JPEG_CTRL 0x0980
#define REG0982_JPEG_STATUS_FLAG 0x0982
#define REG0984_JPEG_RAW_STATUS_FLAG 0x0984
#define REG0986_JPEG_INTERRUPT_CTRL 0x0986
#define REG0988_JPEG_RESET_STATUS 0x0988
#define REG098A_JPEG_STARTSTOP_CTRL 0x098a
// JPEG FILE BUFFER SETTING REGISTERS
#define REG09A0_JPEG_FIFO_CTRL 0x09a0
#define REG09A2_JPEG_FIFO_STATUS 0x09a2
#define REG09A4_JPEG_FIFO_SIZE 0x09a4
#define REG09A6_JPEG_FIFO_RDWR 0x09a6
#define REG09A8_JPEG_FIFO_VALIDDATASIZE 0x09a8
#define REG09AA_JPEG_FIFO_RD_POINTER 0x09aa
#define REG09AC_JPEG_FIFO_WR_POINTER 0x09ac
#define REG09B0_ENCODE_SIZE_LIMIT0 0x09b0
#define REG09B2_ENCODE_SIZE_LIMIT1 0x09b2
#define REG09B4_ENCODE_SIZE_RESULT0 0x09b4
#define REG09B6_ENCODE_SIZE_RESULT1 0x09b6
#define REG09B8_JPEG_FILE_SIZE0 0x09b8
#define REG09BA_JPEG_FILE_SIZE1 0x09ba
#define REG09C0_JPEG_LBUF_STATUS 0x09c0
#define REG09C2_JPEG_LBUF_RAW_STATUS 0x09c2
#define REG09C4_JPEG_LBUF_RAW_CUR_STATUS 0x09c4
#define REG09C6_JPEG_LBUF_INT_CONTROL 0x09c6
#define REG09E0_JPEG_LBUF_WRITE_PORT 0x09e0
// INTERRUPT CONTROL REGISTERS
#define REG0A00_INTERRUPT_STATUS 0x0a00
#define REG0A02_INTERRUPT_CTRL0 0x0a02
#define REG0A04_INTERRUPT_CTRL1 0x0a04
#define REG0A06_DEBUG_STATUS 0x0a06
#define REG0A08_INTERRUPT_CTRL_DEBUG 0x0a08
#define REG0A0A_HOST_INTERRUPT_STATUS 0x0A0A
#define REG0A0C_HOST_INTERRUPT_CONTROL 0x0A0C
#define REG0A0E_CYCLE_TIME_OUT_CONTROL 0x0A0E
#define REG0A10_DEBUG 0x0A10
// JPEG CODEC REGISTERS
#define REG1000_OP_MODE_SETTING 0x1000
#define REG1002_COMMAND_SETTING 0x1002
#define REG1004_JPEG_OP_STATUS 0x1004
#define REG1006_QUANTIZATION_TABLE_NUM 0x1006
#define REG1008_HUFFMAN_TABLE_NUM 0x1008
#define REG100A_DRI_SETTING0 0x100a
#define REG100C_DRI_SETTING1 0x100c
#define REG100E_VERTICAL_PIXEL_SIZE0 0x100e
#define REG1010_VERTICAL_PIXEL_SIZE1 0x1010
#define REG1012_HORIZ_PIXEL_SIZE0 0x1012
#define REG1014_HORIZ_PIXEL_SIZE1 0x1014
#define REG1016_DNL_VALUE_SETTING0 0x1016
#define REG1018_DNL_VALUE_SETTING1 0x1018
#define REG101C_RST_MARKER_OP_SETTING 0x101c
#define REG101E_RST_MARKER_OP_STATUS 0x101e
#define REG1020_INSERTION_MARKER_DATA 0x1020
#define REG1200_QUANTIZATION_TABLE_NO0 0x1200
#define REG1280_QUANTIZATION_TABLE_NO1 0x1280
#define REG1400_DC_HUFFMAN_TABLE0_REG0 0x1400
#define REG1420_DC_HUFFMAN_TABLE0_REG1 0x1420
#define REG1440_AC_HUFFMAN_TABLE0_REG0 0x1440
#define REG1460_AC_HUFFMAN_TABLE0_REG1 0x1460
#define REG1600_DC_HUFFMAN_TABLE1_REG0 0x1600
#define REG1620_DC_HUFFMAN_TABLE1_REG1 0x1620
#define REG1640_AC_HUFFMAN_TABLE1_REG0 0x1640
#define REG1660_AC_HUFFMAN_TABLE1_REG1 0x1660
// 2D ACCELERATION REGISTERS
#define REG_BLT_BASE 0x8000
#define REG8000_BLT_CTRL 0x8000
#define REG8002_BLT_CTRL 0x8002
#define REG8004_BLT_STATUS 0x8004
#define REG8006_BLT_STATUS 0x8006
#define REG8008_BLT_COMMAND 0x8008
#define REG800A_BLT_COMMAND 0x800a
#define REG800C_BLT_SOURCE_START_ADDR0 0x800c
#define REG800E_BLT_SOURCE_START_ADDR1 0x800e
#define REG8010_BLT_DEST_START_ADDR0 0x8010
#define REG8012_BLT_DEST_START_ADDR1 0x8012
#define REG8014_BLT_MEM_ADDR_OFFSET 0x8014
#define REG8018_BLT_WIDTH 0x8018
#define REG801C_BLT_HEIGHT 0x801c
#define REG8020_BLT_BACKGROUND_COLOR 0x8020
#define REG8024_BLT_FOREGROUND_COLOR 0x8024
#define REG8030_BLT_INTERRUPT_STATUS 0x8030
#define REG8032_BLT_INTERRUPT_CTRL 0x8032
#define REG10000_BLT_DATA 0x00010000
#define REG_RESERVED 0xFFF0 // Special reserved flags above this point.
#define REG_POWER_OFF_DELAY 0xFFFD // Indicates a ms delay for powering down LCD.
#define REG_POWER_ON_DELAY 0xFFFE // Indicates a ms delay for powering up LCD.
#define REG_END_OF_TABLE 0xFFFF // End of register table flag.
#endif // __HAL_REG_H__
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