📄 se3208.h

📁 isp1161驱动代码是我下载并该动后而成,还有点缺点,但对你可能有点帮助
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#     define __EXT_WAIT_02_CLK           ( 0 << 0 )#     define __EXT_WAIT_04_CLK           ( 1 << 0 )#     define __EXT_WAIT_06_CLK           ( 2 << 0 )#     define __EXT_WAIT_08_CLK           ( 3 << 0 )#     define __EXT_WAIT_10_CLK           ( 4 << 0 )#     define __EXT_WAIT_12_CLK           ( 5 << 0 )#     define __EXT_WAIT_14_CLK           ( 6 << 0 )#     define __EXT_WAIT_16_CLK           ( 7 << 0 )/**************************************************/// LOCAL DRAM CONTROL REGISTER : 0X0180_0408/**************************************************/#     define __LROM_CONTROL_ACTIVE                  ( 0 << 24 )#     define __LROM_CONTROL_SW_RESET                ( 1 << 24 )#     define __LROM_4_MBYTE_BANK                    ( 0 << 20 )#     define __LROM_8_MBYTE_BANK                    ( 1 << 20 )#     define __LROM_ROW_ADDRESS_11_BIT              ( 0 << 18 )#     define __LROM_ROW_ADDRESS_12_BIT              ( 1 << 18 )#     define __LROM_ROW_ADDRESS_13_BIT              ( 2 << 18 )#     define __LROM_ROW_ADDRESS_14_BIT              ( 3 << 18 )#     define __LROM_COL_ADDRESS_08_BIT              ( 0 << 16 )#     define __LROM_COL_ADDRESS_09_BIT              ( 1 << 16 )#     define __LROM_COL_ADDRESS_10_BIT              ( 2 << 16 )#     define __LROM_COL_ADDRESS_11_BIT              ( 3 << 16 )#     define __LROM_FP_DRAM_LATCH_NORMAL            ( 0 << 13 )#     define __LROM_FP_DRAM_LATCH_DELAY             ( 1 << 13 )#     define __LROM_RAS_TO_CAS_DELAY_1_CLK          ( 0 << 11 )#     define __LROM_RAS_TO_CAS_DELAY_2_CLK          ( 1 << 11 )#     define __LROM_RAS_TO_CAS_DELAY_3_CLK          ( 2 << 11 )#     define __LROM_RAS_PRECHARGE_TIME_1_CLK        ( 0 << 9 )#     define __LROM_RAS_PRECHARGE_TIME_2_CLK        ( 1 << 9 )#     define __LROM_RAS_PRECHARGE_TIME_3_CLK        ( 2 << 9 )#     define __LROM_RAS_PRECHARGE_TIME_4_CLK        ( 3 << 9 )#     define __LROM_CAS_LATENCY_2_CLK               ( 0 << 8 )#     define __LROM_CAS_LATENCY_3_CLK               ( 1 << 8 )#     define __LROM_CAS_PRECHARGE_TIME_1_CLK        ( 0 << 8 )#     define __LROM_CAS_PRECHARGE_TIME_2_CLK        ( 1 << 8 )#     define __LROM_CAS_ACTIVE_PULSE_WIDTH_1_CLK    ( 0 << 6 )#     define __LROM_CAS_ACTIVE_PULSE_WIDTH_2_CLK    ( 2 << 6 )#     define __LROM_SRAM_COMMAND_WIDTH_1_CLK        ( 0 << 6 )#     define __LROM_SRAM_COMMAND_WIDTH_2_CLK        ( 1 << 6 )#     define __LROM_SRAM_COMMAND_WIDTH_3_CLK        ( 2 << 6 )#     define __LROM_SRAM_COMMAND_WIDTH_4_CLK        ( 3 << 6 )#     define __LROM_SDRAM_RAS_CYCLE_TIME_3_CLK      ( 0 << 4 )#     define __LROM_SDRAM_RAS_CYCLE_TIME_4_CLK      ( 1 << 4 )#     define __LROM_SDRAM_RAS_CYCLE_TIME_5_CLK      ( 2 << 4 )#     define __LROM_SDRAM_RAS_CYCLE_TIME_6_CLK      ( 3 << 4 )#     define __LROM_FPEDO_RAS_PULSE_WIDTH_2_CLK     ( 0 << 4 )#     define __LROM_FPEDO_RAS_PULSE_WIDTH_3_CLK     ( 1 << 4 )#     define __LROM_FPEDO_RAS_PULSE_WIDTH_4_CLK     ( 2 << 4 )#     define __LROM_FPEDO_RAS_PULSE_WIDTH_5_CLK     ( 3 << 4 )#     define __LROM_REFRESH_CYCLE_PERIOD_15_6_USEC  ( 0 << 3 )#     define __LROM_REFRESH_CYCLE_PERIOD_31_2_USEC  ( 1 << 3 )#     define __LROM_REFRESH_CYCLE_PERIOD_1_CYCLE    ( 0 << 2 )#     define __LROM_REFRESH_CYCLE_PERIOD_2_CYCLE    ( 1 << 2 )#     define __LROM_TYPE_SRAM                       ( 0 << 0 )#     define __LROM_TYPE_EDO_DRAM                   ( 1 << 0 )#     define __LROM_TYPE_FP_DRAM                    ( 2 << 0 )#     define __LROM_TYPE_SYNC_DRAM                  ( 3 << 0 )/**************************************************/// PCS CONTROL REGISTER/**************************************************/#     define __EXTERNAL_READY_DISABLE    ( 0 << 15 )#     define __EXTERNAL_READY_ENABLE     ( 1 << 15 )#     define __PCS_WAIT_STATE( VALUE )   ( VALUE << 8 )#     define __PCS_DISABLE               ( 0 << 7 )#     define __PCS_ENABLE                ( 1 << 7 )#     define __PCS_DATA_BUS_WIDTH_08     ( 0 << 2 )#     define __PCS_DATA_BUS_WIDTH_16     ( 1 << 2 )#     define __PCS_DATA_BUS_WIDTH_32     ( 2 << 2 )#     define __PCS_DECODE_ADDRESS_ONLY   ( 0 << 0 )#     define __PCS_DECODE_WITH_RDX       ( 2 << 0 )#     define __PCS_DECODE_WITH_WRX       ( 3 << 0 )/**************************************************/// CRTC STATUS / MODE REGISTER/**************************************************/#     define __CRTC_SCREEN_NORMAL                ( 0 << 9 )#     define __CRTC_SCREEN_BLANK                 ( 1 << 9 )#     define __CRTC_WRITE_ENABLE                 ( 0 << 8 )#     define __CRTC_WRITE_DISABLE                ( 1 << 8 )#     define __CRTC_HORI_SCAN_LINE_525           ( 0 << 7 )#     define __CRTC_HORI_SCAN_LINE_625           ( 1 << 7 )#     define __CRTC_COLOR_BURST_FRQ_358          ( 0 << 6 )#     define __CRTC_COLOR_BURST_FRQ_443          ( 1 << 6 )#     define __CRTC_LOCAL_MODE                   ( 0 << 4 )#     define __CRTC_REMOTE_MODE_WITH_PLL         ( 1 << 4 )#     define __CRTC_REMOTE_MODE_NOT_PLL          ( 2 << 4 )#     define __CRTC_REMOTE_MODE_WITH_MC1378      ( 3 << 4 )#     define __CRTC_LUT_LOWER_NTSC_ODD           ( 0 << 3 )#     define __CRTC_LUT_LOWER_NTSC_EVN           ( 1 << 3 )#     define __CRTC_REMOTE_VSYNCIN               ( 0 << 2 )#     define __CRTC_REMOTE_INTERNAL_BLOCK        ( 1 << 2 )#     define __CRTC_VERT_SYNC_SERRATION_ONLY     ( 0 << 0 )#     define __CRTC_VERT_SYNC_POST_SERRATION     ( 1 << 0 )#     define __CRTC_VERT_SYNC_PRE_SERRATION      ( 2 << 0 )#     define __CRTC_VERT_SYNC_PRE_POST_SERRATION ( 3 << 0 )/**************************************************/// CRTC TIMING CONTROL REGISTER/**************************************************/#     define __CRTC_OVEN_VIDEO_CLK_DELAY( VALUE )  ( VALUE << 14 )#     define __CRTC_FSC4CLK_CPCLK                  ( 0 << 13)#     define __CRTC_FSC4CLK_14_3_MHZ               ( 1 << 13)#     define __CRTC_CBF_POL_ACTIVE_LOW             ( 0 << 12)#     define __CRTC_CBF_POL_ACTIVE_HIGH            ( 1 << 12)#     define __CRTC_OVEN_POL_ACTIVE_LOW            ( 0 << 11)#     define __CRTC_OVEN_POL_ACTIVE_HIGH           ( 1 << 11)#     define __CRTC_OVEN_DOT_CLK_DELAY( VALUE )    ( VALUE << 8 )#     define __CRTC_VCLK_1X                        ( 1 << 7 )#     define __CRTC_VCLK_2X                        ( 1 << 7 )#     define __CRTC_VCLK_14_MHZ                    ( 0 << 4 )#     define __CRTC_VCLK_21_MHZ                    ( 1 << 4 )#     define __CRTC_VCLK_28_MHZ                    ( 2 << 4 )#     define __CRTC_VCLK_35_MHZ                    ( 3 << 4 )#     define __CRTC_VCLK_42_MHZ                    ( 4 << 4 )#     define __CRTC_VCLK_50_MHZ                    ( 5 << 4 )#     define __CRTC_VCLK_57_MHZ                    ( 6 << 4 )#     define __CRTC_VCLK_64_MHZ                    ( 7 << 4 )#     define __CRTC_DCLK_1_0_DIV                   ( 0 << 0 )#     define __CRTC_DCLK_1_5_DIV                   ( 1 << 0 )#     define __CRTC_DCLK_2_0_DIV                   ( 2 << 0 )#     define __CRTC_DCLK_2_5_DIV                   ( 3 << 0 )#     define __CRTC_DCLK_3_0_DIV                   ( 4 << 0 )#     define __CRTC_DCLK_3_5_DIV                   ( 5 << 0 )#     define __CRTC_DCLK_4_0_DIV                   ( 6 << 0 )#     define __CRTC_DCLK_4_5_DIV                   ( 7 << 0 )/**************************************************/// HORIZONTAL SYNC WIDTH / BACK PORCH REGISTER/**************************************************/#     define __CRTC_HORI_BACK_PORCH( VALUE )  ( VALUE << 8 )#     define __CRTC_HORI_SYNC_WIDTH( VALUE )  ( VALUE << 0 )/**************************************************/// HORIZONTAL SYNC FRONT PORCH REGISTER/**************************************************/#     define __CRTC_NTSC_PERIOD_TEST1_0        ( 0 << 9 )#     define __CRTC_NTSC_PERIOD_TEST1_1        ( 1 << 9 )#     define __CRTC_NTSC_NUMBER_TEST0_0        ( 0 << 8 )#     define __CRTC_NTSC_NUMBER_TEST0_1        ( 1 << 8 )#     define __CRTC_HORI_FRONT_PORCH( VALUE )  ( VALUE << 0 )/**************************************************/// FIELD WINDOW BOUND REGISTER /**************************************************/#     define __CRTC_EVEN_FIELD_FROM_HSYNC_BLOCK  ( 0 << 14 )#     define __CRTC_EVEN_FIELD_FROM_SYNCTOVH     ( 1 << 14 )#     define __CRTC_WINDOW_UPPER_BOUND( VALUE )  ( VALUE << 8 )#     define __CRTC_WINDOW_LOWER_BOUND( VALUE )  ( VALUE << 0 )/**************************************************/// RAMDAC & PLL CONTROL REGISTER/**************************************************/#     define __POWER_SAVING_DAC_NORMAL     ( 0 << 9 )#     define __POWER_SAVING_DAC_ENABLE     ( 1 << 9 )#     define __PALETTE_CPU_ACCESS_DISABLE  ( 0 << 8 )#     define __PALETTE_CPU_ACCESS_ENABLE   ( 0 << 8 )#     define __WRITE_PLL_REGISTER_DISABLE  ( 0 << 2 )#     define __WRITE_PLL_REGISTER_ENABLE   ( 1 << 2 )#     define __MAIN_CLOCK_SELECT_PLL_CLK   ( 0 << 1 )#     define __MAIN_CLOCK_SELECT_EXT_CLK   ( 1 << 1 )#     define __POWER_SAVING_PLL_NORMAL     ( 0 << 0 )#     define __POWER_SAVING_PLL_ENABLE     ( 1 << 0 )/**************************************************/// PLL PROGRAM REGISTER/**************************************************/#     define __PLL_PROGRAM_MAIN_DIVIDER ( VALUE )  ( VALUE << 8 )#     define __PLL_PROGRAM_PRE_DIVIDER ( VALUE )   ( VALUE << 2 )#     define __PLL_PROGRAM_POST_DIVIDER ( VALUE )  ( VALUE << 0 )//############################################################################define __CACHE_INVALIDATE_SET(VALUE)				\                  asm( "CACHE_INVALIDATE_SET: ");		\		  asm( "push %R0");				\		  asm( "ldi  %0   , %%R0" : : "i" (VALUE) );	\		  asm( "mvtc  0   , %CR5");			\		  asm( "pop  %R0");		  #define __CACHE_INVALIDATE_CHECK()				\                  asm( "CACHE_INVALIDATE_CHECK:");		\                  asm( "mvfc  0  , %CR6");			\                  asm( "and  %R0, 0x00100000, %R0");		\                  asm( "jnz   CACHE_INVALIDATE_CHECK"); #define __CACHE_MODE_SET(VALUE)					\                  asm( "CACHE_MODE_SET: ");			\		  asm( "push %R0");				\		  asm( "ldi  %0   , %%R0" : : "i" (VALUE) );	\		  asm( "mvtc  0   , %CR3");			\		  asm( "pop  %R0");#define __CACHE_ACTIVE_SET(VALUE)				\                  asm( "CACHE_ACTIVE_SET: ");			\		  asm( "push %R0");				\		  asm( "ldi  %0   , %%R0" : : "i" (VALUE) );	\		  asm( "mvtc  0   , %CR7");			\		  asm( "pop  %R0");		  /**************************************************/// CACHE MASTER COMMAND REGISTER/**************************************************/#     define __CACHE_UNIT_DISABLE          ( 0 << 11 )#     define __CACHE_UNIT_ENABLE           ( 1 << 11 )#     define __CACHE_UNIT_NORMAL           ( 0 << 0 )#     define __CACHE_UNIT_DELAY            ( 1 << 0 )/**************************************************/// CACHE INVALIDATE REGISTER/**************************************************/#     define __CACHE_INVALIDATE_DISABLE   ( 0 << 0 )#     define __CACHE_INVALIDATE_ENABLE    ( 1 << 0 )		  /**************************************************/// CACHE INVALIDATE REGISTER/**************************************************/#     define __CACHE_WRITE_THROUGH        ( 0 << 6 )#     define __CACHE_WRITE_BACK           ( 1 << 6 )//############################################################################endif		/*  se3208.h  */
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