📄 ppc_860.h
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cyg_uint32 itemp1; /* Temp Data Storage */ cyg_uint32 itemp2; /* Temp Data Storage */ cyg_uint32 itemp3; /* Temp Data Storage */ cyg_uint32 sr_mem; /* Data Storage for Peripherial Write */ cyg_uint16 read_sp; /* No description given in manual */ cyg_uint16 nodesc0; /* Diff Between Source and Destination Residue*/ cyg_uint16 nodesc1; /* Temp Storage Address Pointer */ cyg_uint16 nodesc2; /* SR_MEM Byte Count */ cyg_uint32 d_state; /* Internal State */};/*--------------------------------------------------------------------------*//* RISC timer parameter RAM *//*--------------------------------------------------------------------------*/struct timer_pram { /*----------------------------*/ /* RISC timers parameter RAM */ /*----------------------------*/ cyg_uint16 tm_base; /* RISC timer table base adr */ cyg_uint16 tm_ptr; /* RISC timer table pointer */ cyg_uint16 r_tmr; /* RISC timer mode register */ cyg_uint16 r_tmv; /* RISC timer valid register */ cyg_uint32 tm_cmd; /* RISC timer cmd register */ cyg_uint32 tm_cnt; /* RISC timer internal cnt */};/*--------------------------------------------------------------------------*//* ROM Microcode parameter RAM *//*--------------------------------------------------------------------------*/struct ucode_pram { /*---------------------------*/ /* RISC ucode parameter RAM */ /*---------------------------*/ cyg_uint16 rev_num; /* Ucode Revision Number */ cyg_uint16 d_ptr; /* MISC Dump area pointer */ cyg_uint32 temp1; /* MISC Temp1 */ cyg_uint32 temp2; /* MISC Temp2 */};/*---------------------------------------------------------------------------*//* Example structuring of user data area of memory at 0x2000 (base of DPRAM) *//* Note that this area can also be used by microcodes and the QMC channel *//* specific parameter ram. *//*---------------------------------------------------------------------------*/struct user_data{ volatile cyg_uint8 udata_bd_ucode[0x200]; /* user data bd's or Ucode (small) */ volatile cyg_uint8 udata_bd_ucode2[0x200]; /* user data bd's or Ucode (medium) */ volatile cyg_uint8 udata_bd_ucode3[0x400]; /* user data bd's or Ucode (large) */ volatile cyg_uint8 udata_bd[0x700]; /* user data bd's*/ volatile cyg_uint8 ucode_ext[0x100]; /* Ucode Extension ram*/ volatile cyg_uint8 RESERVED12[0x0c00]; /* Reserved area */};/***************************************************************************//* *//* Definitions of Embedded PowerPC (EPPC) internal memory structures, *//* including registers and dual-port RAM *//* *//***************************************************************************/typedef struct eppc { /*-----------------------------------*/ /* BASE + 0x0000: INTERNAL REGISTERS */ /*-----------------------------------*/ /*-----*/ /* SIU */ /*-----*/ volatile cyg_uint32 siu_mcr; /* module configuration reg */ volatile cyg_uint32 siu_sypcr; /* System protection cnt */ cyg_uint8 RESERVED13[0x6]; volatile cyg_uint16 siu_swsr; /* sw service */ volatile cyg_uint32 siu_sipend; /* Interrupt pend reg */ volatile cyg_uint32 siu_simask; /* Interrupt mask reg */ volatile cyg_uint32 siu_siel; /* Interrupt edge level mask reg */ volatile cyg_uint32 siu_sivec; /* Interrupt vector */ volatile cyg_uint32 siu_tesr; /* Transfer error status */ volatile cyg_uint8 RESERVED14[0xc]; /* Reserved area */ volatile cyg_uint32 dma_sdcr; /* SDMA configuration reg */ cyg_uint8 RESERVED15[0x4c]; /*--------*/ /* PCMCIA */ /*--------*/ volatile cyg_uint32 pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */ volatile cyg_uint32 pcmcia_por0; /* PCMCIA Option Reg: Window 0 */ volatile cyg_uint32 pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */ volatile cyg_uint32 pcmcia_por1; /* PCMCIA Option Reg: Window 1 */ volatile cyg_uint32 pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */ volatile cyg_uint32 pcmcia_por2; /* PCMCIA Option Reg: Window 2 */ volatile cyg_uint32 pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */ volatile cyg_uint32 pcmcia_por3; /* PCMCIA Option Reg: Window 3 */ volatile cyg_uint32 pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */ volatile cyg_uint32 pcmcia_por4; /* PCMCIA Option Reg: Window 4 */ volatile cyg_uint32 pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */ volatile cyg_uint32 pcmcia_por5; /* PCMCIA Option Reg: Window 5 */ volatile cyg_uint32 pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */ volatile cyg_uint32 pcmcia_por6; /* PCMCIA Option Reg: Window 6 */ volatile cyg_uint32 pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */ volatile cyg_uint32 pcmcia_por7; /* PCMCIA Option Reg: Window 7 */ volatile cyg_uint8 RESERVED16[0x20]; /* Reserved area */ volatile cyg_uint32 pcmcia_pgcra; /* PCMCIA Slot A Control Reg */ volatile cyg_uint32 pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */ volatile cyg_uint32 pcmcia_pscr; /* PCMCIA Status Reg */ volatile cyg_uint8 RESERVED17[0x4]; /* Reserved area */ volatile cyg_uint32 pcmcia_pipr; /* PCMCIA Pins Value Reg */ volatile cyg_uint8 RESERVED18[0x4]; /* Reserved area */ volatile cyg_uint32 pcmcia_per; /* PCMCIA Enable Reg */ volatile cyg_uint8 RESERVED19[0x4]; /* Reserved area */ /*------*/ /* MEMC */ /*------*/ volatile cyg_uint32 memc_br0; /* base register 0 */ volatile cyg_uint32 memc_or0; /* option register 0 */ volatile cyg_uint32 memc_br1; /* base register 1 */ volatile cyg_uint32 memc_or1; /* option register 1 */ volatile cyg_uint32 memc_br2; /* base register 2 */ volatile cyg_uint32 memc_or2; /* option register 2 */ volatile cyg_uint32 memc_br3; /* base register 3 */ volatile cyg_uint32 memc_or3; /* option register 3 */ volatile cyg_uint32 memc_br4; /* base register 3 */ volatile cyg_uint32 memc_or4; /* option register 3 */ volatile cyg_uint32 memc_br5; /* base register 3 */ volatile cyg_uint32 memc_or5; /* option register 3 */ volatile cyg_uint32 memc_br6; /* base register 3 */ volatile cyg_uint32 memc_or6; /* option register 3 */ volatile cyg_uint32 memc_br7; /* base register 3 */ volatile cyg_uint32 memc_or7; /* option register 3 */ volatile cyg_uint8 RESERVED20[0x24]; /* Reserved area */ volatile cyg_uint32 memc_mar; /* Memory address */ volatile cyg_uint32 memc_mcr; /* Memory command */ volatile cyg_uint8 RESERVED21[0x4]; /* Reserved area */ volatile cyg_uint32 memc_mamr; /* Machine A mode */ volatile cyg_uint32 memc_mbmr; /* Machine B mode */ volatile cyg_uint16 memc_mstat; /* Memory status */ volatile cyg_uint16 memc_mptpr; /* Memory preidic timer prescalar */ volatile cyg_uint32 memc_mdr; /* Memory data */ volatile cyg_uint8 RESERVED22[0x80]; /* Reserved area */ /*---------------------------*/ /* SYSTEM INTEGRATION TIMERS */ /*---------------------------*/ volatile cyg_uint16 simt_tbscr; /* Time base stat&ctr */ volatile cyg_uint8 RESERVED23[0x2]; /* Reserved area */ volatile cyg_uint32 simt_tbreff0; /* Time base reference 0 */ volatile cyg_uint32 simt_tbreff1; /* Time base reference 1 */ volatile cyg_uint8 RESERVED24[0x14]; /* Reserved area */ volatile cyg_uint16 simt_rtcsc; /* Realtime clk stat&cntr 1 */ volatile cyg_uint8 RESERVED25[0x2]; /* Reserved area */ volatile cyg_uint32 simt_rtc; /* Realtime clock */ volatile cyg_uint32 simt_rtsec; /* Realtime alarm seconds */ volatile cyg_uint32 simt_rtcal; /* Realtime alarm */ volatile cyg_uint8 RESERVED26[0x10]; /* Reserved area */ volatile cyg_uint32 simt_piscr; /* PIT stat&ctrl */ volatile cyg_uint32 simt_pitc; /* PIT counter */ volatile cyg_uint32 simt_pitr; /* PIT */ volatile cyg_uint8 RESERVED27[0x34]; /* Reserved area */ /*---------------*/ /* CLOCKS, RESET */ /*---------------*/ volatile cyg_uint32 clkr_sccr; /* System clk cntrl */ volatile cyg_uint32 clkr_plprcr; /* PLL reset&ctrl */ volatile cyg_uint32 clkr_rsr; /* reset status */ cyg_uint8 RESERVED28[0x74]; /* Reserved area */ /*--------------------------------*/ /* System Integration Timers Keys */ /*--------------------------------*/ volatile cyg_uint32 simt_tbscrk; /* Timebase Status&Ctrl Key */ volatile cyg_uint32 simt_tbreff0k; /* Timebase Reference 0 Key */ volatile cyg_uint32 simt_tbreff1k; /* Timebase Reference 1 Key */ volatile cyg_uint32 simt_tbk; /* Timebase and Decrementer Key */ cyg_uint8 RESERVED29[0x10]; /* Reserved area */ volatile cyg_uint32 simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */ volatile cyg_uint32 simt_rtck; /* Real-Time Clock Key */ volatile cyg_uint32 simt_rtseck; /* Real-Time Alarm Seconds Key */ volatile cyg_uint32 simt_rtcalk; /* Real-Time Alarm Key */ cyg_uint8 RESERVED30[0x10]; /* Reserved area */ volatile cyg_uint32 simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */ volatile cyg_uint32 simt_pitck; /* Periodic Interrupt Count Key */ cyg_uint8 RESERVED31[0x38]; /* Reserved area */ /*----------------------*/ /* Clock and Reset Keys */ /*----------------------*/ volatile cyg_uint32 clkr_sccrk; /* System Clock Control Key */ volatile cyg_uint32 clkr_plprcrk; /* PLL, Low Power and Reset Control Key */ volatile cyg_uint32 clkr_rsrk; /* Reset Status Key */ cyg_uint8 RESERVED32[0x4d4]; /* Reserved area */ /*-----*/ /* I2C */ /*-----*/ volatile cyg_uint8 i2c_i2mod; /* i2c mode */ cyg_uint8 RESERVED33[3]; volatile cyg_uint8 i2c_i2add; /* i2c address */ cyg_uint8 RESERVED34[3]; volatile cyg_uint8 i2c_i2brg; /* i2c brg */ cyg_uint8 RESERVED35[3]; volatile cyg_uint8 i2c_i2com; /* i2c command */ cyg_uint8 RESERVED36[3]; volatile cyg_uint8 i2c_i2cer; /* i2c event */ cyg_uint8 RESERVED37[3]; volatile cyg_uint8 i2c_i2cmr; /* i2c mask */ volatile cyg_uint8 RESERVED38[0x8b]; /* Reserved area */ /*-----*/ /* DMA */ /*-----*/ volatile cyg_uint8 RESERVED39[0x4]; /* Reserved area */ volatile cyg_uint32 dma_sdar; /* SDMA address reg */ volatile cyg_uint8 RESERVED40[0x2]; /* Reserved area */ volatile cyg_uint8 dma_sdsr; /* SDMA status reg */ volatile cyg_uint8 RESERVED41[0x3]; /* Reserved area */ volatile cyg_uint8 dma_sdmr; /* SDMA mask reg */ volatile cyg_uint8 RESERVED42[0x1]; /* Reserved area */ volatile cyg_uint8 dma_idsr1; /* IDMA1 status reg */ volatile cyg_uint8 RESERVED43[0x3]; /* Reserved area */ volatile cyg_uint8 dma_idmr1; /* IDMA1 mask reg */ volatile cyg_uint8 RESERVED44[0x3]; /* Reserved area */ volatile cyg_uint8 dma_idsr2; /* IDMA2 status reg */ volatile cyg_uint8 RESERVED45[0x3]; /* Reserved area */ volatile cyg_uint8 dma_idmr2; /* IDMA2 mask reg */ volatile cyg_uint8 RESERVED46[0x13]; /* Reserved area */ /*--------------------------*/ /* CPM Interrupt Controller */ /*--------------------------*/ volatile cyg_uint16 cpmi_civr; /* CP interrupt vector reg */ volatile cyg_uint8 RESERVED47[0xe]; /* Reserved area */ volatile cyg_uint32 cpmi_cicr; /* CP interrupt configuration reg */ volatile cyg_uint32 cpmi_cipr; /* CP interrupt pending reg */ volatile cyg_uint32 cpmi_cimr; /* CP interrupt mask reg */ volatile cyg_uint32 cpmi_cisr; /* CP interrupt in-service reg */ /*----------*/ /* I/O port */ /*----------*/ volatile cyg_uint16 pio_padir; /* port A data direction reg */ volatile cyg_uint16 pio_papar; /* port A pin assignment reg */ volatile cyg_uint16 pio_paodr; /* port A open drain reg */ volatile cyg_uint16 pio_padat; /* port A data register */ volatile cyg_uint8 RESERVED48[0x8]; /* Reserved area */ volatile cyg_uint16 pio_pcdir; /* port C data direction reg */ volatile cyg_uint16 pio_pcpar; /* port C pin assignment reg */ volatile cyg_uint16 pio_pcso; /* port C special options */ volatile cyg_uint16 pio_pcdat; /* port C data register */ volatile cyg_uint16 pio_pcint; /* port C interrupt cntrl reg */ cyg_uint8 RESERVED49[6]; volatile cyg_uint16 pio_pddir; /* port D Data Direction reg */ volatile cyg_uint16 pio_pdpar; /* port D pin assignment reg */ cyg_uint8 RESERVED50[2]; volatile cyg_uint16 pio_pddat; /* port D data reg */ volatile cyg_uint8 RESERVED51[0x8]; /* Reserved area */ /*-----------*/ /* CPM Timer */ /*-----------*/ volatile cyg_uint16 timer_tgcr; /* timer global configuration reg */ volatile cyg_uint8 RESERVED52[0xe]; /* Reserved area */ volatile cyg_uint16 timer_tmr1; /* timer 1 mode reg */ volatile cyg_uint16 timer_tmr2; /* timer 2 mode reg */ volatile cyg_uint16 timer_trr1; /* timer 1 referance reg */ volatile cyg_uint16 timer_trr2; /* timer 2 referance reg */ volatile cyg_uint16 timer_tcr1; /* timer 1 capture reg */ volatile cyg_uint16 timer_tcr2; /* timer 2 capture reg */ volatile cyg_uint16 timer_tcn1; /* timer 1 counter reg */ volatile cyg_uint16 timer_tcn2; /* timer 2 counter reg */ volatile cyg_uint16 timer_tmr3; /* timer 3 mode reg */ volatile cyg_uint16 timer_tmr4; /* timer 4 mode reg */ volatile cyg_uint16 timer_trr3; /* timer 3 referance reg */ volatile cyg_uint16 timer_trr4; /* timer 4 referance reg */ volatile cyg_uint16 timer_tcr3; /* timer 3 capture reg */ volatile cyg_uint16 timer_tcr4; /* timer 4 capture reg */ volatile cyg_uint16 timer_tcn3; /* timer 3 counter reg */ volatile cyg_uint16 timer_tcn4; /* timer 4 counter reg */ volatile cyg_uint16 timer_ter1; /* timer 1 event reg */ volatile cyg_uint16 timer_ter2; /* timer 2 event reg */ volatile cyg_uint16 timer_ter3; /* timer 3 event reg */ volatile cyg_uint16 timer_ter4; /* timer 4 event reg */ volatile cyg_uint8 RESERVED53[0x8]; /* Reserved area */ /*----*/ /* CP */ /*----*/ volatile cyg_uint16 cp_cr; /* command register */ volatile cyg_uint8 RESERVED54[0x2]; /* Reserved area */ volatile cyg_uint16 cp_rccr; /* main configuration reg */⌨️ 快捷键说明
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