📄 ppc_860.h
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cyg_uint32 rcrc; /* temp receive CRC */ cyg_uint32 tcrc; /* temp transmit CRC */ /*---------------------------------*/ /* ETHERNET specific parameter RAM */ /*---------------------------------*/ cyg_uint32 c_pres; /* preset CRC */ cyg_uint32 c_mask; /* constant mask for CRC */ cyg_uint32 crcec; /* CRC error counter */ cyg_uint32 alec; /* alighnment error counter */ cyg_uint32 disfc; /* discard frame counter */ cyg_uint16 pads; /* short frame PAD characters */ cyg_uint16 ret_lim; /* retry limit threshold */ cyg_uint16 ret_cnt; /* retry limit counter */ cyg_uint16 mflr; /* maximum frame length reg */ cyg_uint16 minflr; /* minimum frame length reg */ cyg_uint16 maxd1; /* maximum DMA1 length reg */ cyg_uint16 maxd2; /* maximum DMA2 length reg */ cyg_uint16 maxd; /* rx max DMA */ cyg_uint16 dma_cnt; /* rx dma counter */ cyg_uint16 max_b; /* max bd byte count */ cyg_uint16 gaddr1; /* group address filter 1 */ cyg_uint16 gaddr2; /* group address filter 2 */ cyg_uint16 gaddr3; /* group address filter 3 */ cyg_uint16 gaddr4; /* group address filter 4 */ cyg_uint32 tbuf0_data0; /* save area 0 - current frm */ cyg_uint32 tbuf0_data1; /* save area 1 - current frm */ cyg_uint32 tbuf0_rba0; cyg_uint32 tbuf0_crc; cyg_uint16 tbuf0_bcnt; cyg_uint16 paddr_h; /* physical address (MSB) */ cyg_uint16 paddr_m; /* physical address */ cyg_uint16 paddr_l; /* physical address (LSB) */ cyg_uint16 p_per; /* persistence */ cyg_uint16 rfbd_ptr; /* rx first bd pointer */ cyg_uint16 tfbd_ptr; /* tx first bd pointer */ cyg_uint16 tlbd_ptr; /* tx last bd pointer */ cyg_uint32 tbuf1_data0; /* save area 0 - next frame */ cyg_uint32 tbuf1_data1; /* save area 1 - next frame */ cyg_uint32 tbuf1_rba0; cyg_uint32 tbuf1_crc; cyg_uint16 tbuf1_bcnt; cyg_uint16 tx_len; /* tx frame length counter */ cyg_uint16 iaddr1; /* individual address filter 1*/ cyg_uint16 iaddr2; /* individual address filter 2*/ cyg_uint16 iaddr3; /* individual address filter 3*/ cyg_uint16 iaddr4; /* individual address filter 4*/ cyg_uint16 boff_cnt; /* back-off counter */ cyg_uint16 taddr_h; /* temp address (MSB) */ cyg_uint16 taddr_m; /* temp address */ cyg_uint16 taddr_l; /* temp address (LSB) */};/*------------------------------------------------------------------*//* QMC definitions *//*------------------------------------------------------------------*/struct global_qmc_pram { cyg_uint32 mcbase; /* Multichannel Base pointer */ cyg_uint16 qmcstate; /* Multichannel Controller state */ cyg_uint16 mrblr; /* Maximum Receive Buffer Length */ cyg_uint16 tx_s_ptr; /* TSATTx Pointer */ cyg_uint16 rxptr; /* Current Time slot entry in TSATRx */ cyg_uint16 grfthr; /* Global Receive frame threshold */ cyg_uint16 grfcnt; /* Global Receive Frame Count */ cyg_uint32 intbase; /* Multichannel Base address */ cyg_uint32 intptr; /* Pointer to interrupt queue */ cyg_uint16 rx_s_ptr; /* TSATRx Pointer */ cyg_uint16 txptr; /* Current Time slot entry in TSATTx */ cyg_uint32 c_mask32; /* CRC Constant (debb20e3) */ cyg_uint16 tsatrx[32]; /* Time Slot Assignment Table Rx */ cyg_uint16 tsattx[32]; /* Time Slot Assignment Table Tx */ cyg_uint16 c_mask16; /* CRC Constant (f0b8) */}; /*------------------------------------------*/ /* QMC HDLC channel specific parameter RAM */ /*------------------------------------------*/struct qmc_hdlc_pram { cyg_uint16 tbase; /* Tx Buffer Descriptors Base Address */ cyg_uint16 chamr; /* Channel Mode Register */ cyg_uint32 tstate; /* Tx Internal State */ cyg_uint32 txintr; /* Tx Internal Data Pointer */ cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */ cyg_uint16 txcntr; /* Tx Internal Byte Count */ cyg_uint32 tupack; /* (Tx Temp) */ cyg_uint32 zistate; /* Zero Insertion machine state */ cyg_uint32 tcrc; /* Temp Transmit CRC */ cyg_uint16 intmsk; /* Channel's interrupt mask flags */ cyg_uint16 bdflags; cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */ cyg_uint16 mflr; /* Max Frame Length Register */ cyg_uint32 rstate; /* Rx Internal State */ cyg_uint32 rxintr; /* Rx Internal Data Pointer */ cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */ cyg_uint16 rxbyc; /* Rx Internal Byte Count */ cyg_uint32 rpack; /* (Rx Temp) */ cyg_uint32 zdstate; /* Zero Deletion machine state */ cyg_uint32 rcrc; /* Temp Transmit CRC */ cyg_uint16 maxc; /* Max_length counter */ cyg_uint16 tmp_mb; /* Temp */}; /*-------------------------------------------------*/ /* QMC Transparent channel specific parameter RAM */ /*-------------------------------------------------*/struct qmc_tran_pram { cyg_uint16 tbase; /* Tx Bufer Descriptors Base Address */ cyg_uint16 chamr; /* Channel Mode Register */ cyg_uint32 tstate; /* Tx Internal State */ cyg_uint32 txintr; /* Tx Internal Data Pointer */ cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */ cyg_uint16 txcntr; /* Tx Internal Byte Count */ cyg_uint32 tupack; /* (Tx Temp) */ cyg_uint32 zistate; /* Zero Insertion machine state */ cyg_uint32 RESERVED8; cyg_uint16 intmsk; /* Channel's interrupt mask flags */ cyg_uint16 bdflags; cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */ cyg_uint16 tmrblr; /* Max receive buffer length */ cyg_uint32 rstate; /* Rx Internal State */ cyg_uint32 rxintr; /* Rx Internal Data Pointer */ cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */ cyg_uint16 rxbyc; /* Rx Internal Byte Count */ cyg_uint32 rpack; /* (Rx Temp) */ cyg_uint32 zdstate; /* Zero Deletion machine state */ cyg_uint32 RESERVED9; /* Temp Transmit CRC */ cyg_uint16 trnsync; /* Max_length counter */ cyg_uint16 RESERVED10; /* Temp */};/*----------------------------------------------------------*//* allows multiprotocol array declaration in the memory map *//*----------------------------------------------------------*/struct qmc_chan_pram{ union { struct qmc_hdlc_pram h; struct qmc_tran_pram t; }h_or_t;};/*--------------------------------------------------------------------*//* SMC UART parameter RAM *//*--------------------------------------------------------------------*/struct smc_uart_pram { cyg_uint16 rbase; /* Rx BD Base Address */ cyg_uint16 tbase; /* Tx BD Base Address */ cyg_uint8 rfcr; /* Rx function code */ cyg_uint8 tfcr; /* Tx function code */ cyg_uint16 mrblr; /* Rx buffer length */ cyg_uint32 rstate; /* Rx internal state */ cyg_uint32 rptr; /* Rx internal data pointer */ cyg_uint16 rbptr; /* rb BD Pointer */ cyg_uint16 rcount; /* Rx internal byte count */ cyg_uint32 rtemp; /* Rx temp */ cyg_uint32 tstate; /* Tx internal state */ cyg_uint32 tptr; /* Tx internal data pointer */ cyg_uint16 tbptr; /* Tx BD pointer */ cyg_uint16 tcount; /* Tx byte count */ cyg_uint32 ttemp; /* Tx temp */ cyg_uint16 max_idl; /* Maximum IDLE Characters */ cyg_uint16 idlc; /* Temporary IDLE Counter */ cyg_uint16 brkln; /* Last Rx Break Length */ cyg_uint16 brkec; /* Rx Break Condition Counter */ cyg_uint16 brkcr; /* Break Count Register (Tx) */ cyg_uint16 r_mask; /* Temporary bit mask */};/*--------------------------------------------------------------------------*//* SMC Transparent mode parameter RAM *//*--------------------------------------------------------------------------*/struct smc_trnsp_pram { cyg_uint16 rbase; /* Rx BD Base Address */ cyg_uint16 tbase; /* Tx BD Base Address */ cyg_uint8 rfcr; /* Rx function code */ cyg_uint8 tfcr; /* Tx function code */ cyg_uint16 mrblr; /* Rx buffer length */ cyg_uint32 rstate; /* Rx internal state */ cyg_uint32 rptr; /* Rx internal data pointer */ cyg_uint16 rbptr; /* rb BD Pointer */ cyg_uint16 rcount; /* Rx internal byte count */ cyg_uint32 rtemp; /* Rx temp */ cyg_uint32 tstate; /* Tx internal state */ cyg_uint32 tptr; /* Tx internal data pointer */ cyg_uint16 tbptr; /* Tx BD pointer */ cyg_uint16 tcount; /* Tx byte count */ cyg_uint32 ttemp; /* Tx temp */ cyg_uint16 RESERVED11[5]; /* Reserved */};/*--------------------------------------------------------------------------*//* SPI parameter RAM *//*--------------------------------------------------------------------------*/#define SPI_R 0x8000 /* Ready bit in BD */struct spi_pram { cyg_uint16 rbase; /* Rx BD Base Address */ cyg_uint16 tbase; /* Tx BD Base Address */ cyg_uint8 rfcr; /* Rx function code */ cyg_uint8 tfcr; /* Tx function code */ cyg_uint16 mrblr; /* Rx buffer length */ cyg_uint32 rstate; /* Rx internal state */ cyg_uint32 rptr; /* Rx internal data pointer */ cyg_uint16 rbptr; /* rb BD Pointer */ cyg_uint16 rcount; /* Rx internal byte count */ cyg_uint32 rtemp; /* Rx temp */ cyg_uint32 tstate; /* Tx internal state */ cyg_uint32 tptr; /* Tx internal data pointer */ cyg_uint16 tbptr; /* Tx BD pointer */ cyg_uint16 tcount; /* Tx byte count */ cyg_uint32 ttemp; /* Tx temp */};/*--------------------------------------------------------------------------*//* I2C parameter RAM *//*--------------------------------------------------------------------------*/struct i2c_pram { /*--------------------*/ /* I2C parameter RAM */ /*--------------------*/ cyg_uint16 rbase; /* RX BD base address */ cyg_uint16 tbase; /* TX BD base address */ cyg_uint8 rfcr; /* Rx function code */ cyg_uint8 tfcr; /* Tx function code */ cyg_uint16 mrblr; /* Rx buffer length */ cyg_uint32 rstate; /* Rx internal state */ cyg_uint32 rptr; /* Rx internal data pointer */ cyg_uint16 rbptr; /* rb BD Pointer */ cyg_uint16 rcount; /* Rx internal byte count */ cyg_uint32 rtemp; /* Rx temp */ cyg_uint32 tstate; /* Tx internal state */ cyg_uint32 tptr; /* Tx internal data pointer */ cyg_uint16 tbptr; /* Tx BD pointer */ cyg_uint16 tcount; /* Tx byte count */ cyg_uint32 ttemp; /* Tx temp */};/*--------------------------------------------------------------------------*//* PIP Centronics parameter RAM *//*--------------------------------------------------------------------------*/struct centronics_pram { cyg_uint16 rbase; /* Rx BD Base Address */ cyg_uint16 tbase; /* Tx BD Base Address */ cyg_uint8 fcr; /* function code */ cyg_uint8 smask; /* Status Mask */ cyg_uint16 mrblr; /* Rx buffer length */ cyg_uint32 rstate; /* Rx internal state */ cyg_uint32 rptr; /* Rx internal data pointer */ cyg_uint16 rbptr; /* rb BD Pointer */ cyg_uint16 rcount; /* Rx internal byte count */ cyg_uint32 rtemp; /* Rx temp */ cyg_uint32 tstate; /* Tx internal state */ cyg_uint32 tptr; /* Tx internal data pointer */ cyg_uint16 tbptr; /* Tx BD pointer */ cyg_uint16 tcount; /* Tx byte count */ cyg_uint32 ttemp; /* Tx temp */ cyg_uint16 max_sl; /* Maximum Silence period */ cyg_uint16 sl_cnt; /* Silence Counter */ cyg_uint16 char1; /* CONTROL char 1 */ cyg_uint16 char2; /* CONTROL char 2 */ cyg_uint16 char3; /* CONTROL char 3 */ cyg_uint16 char4; /* CONTROL char 4 */ cyg_uint16 char5; /* CONTROL char 5 */ cyg_uint16 char6; /* CONTROL char 6 */ cyg_uint16 char7; /* CONTROL char 7 */ cyg_uint16 char8; /* CONTROL char 8 */ cyg_uint16 rccm; /* Rx Control Char Mask */ cyg_uint16 rccr; /* Rx Char Control Register */};/*--------------------------------------------------------------------------*//* IDMA parameter RAM *//*--------------------------------------------------------------------------*/struct idma_pram { cyg_uint16 ibase; /* IDMA BD Base Address */ cyg_uint16 dcmr; /* DMA Channel Mode Register */ cyg_uint32 sapr; /* Source Internal Data Pointer */ cyg_uint32 dapr; /* Destination Internal Data Pointer */ cyg_uint16 ibptr; /* Buffer Descriptor Pointer */ cyg_uint16 write_sp; /* No description given in manual */ cyg_uint32 s_byte_c; /* Internal Source Byte Count */ cyg_uint32 d_byte_c; /* Internal Destination Byte Count */ cyg_uint32 s_state; /* Internal State */ cyg_uint32 itemp0; /* Temp Data Storage */⌨️ 快捷键说明
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